[llvm] r182048 - Mips assembler: Add TwoOperandConstraint definitions
Jack Carter
jack.carter at imgtec.com
Thu May 16 13:24:27 PDT 2013
Author: jacksprat
Date: Thu May 16 15:24:27 2013
New Revision: 182048
URL: http://llvm.org/viewvc/llvm-project?rev=182048&view=rev
Log:
Mips assembler: Add TwoOperandConstraint definitions
This patch removes alias definition for addiu $rs,$imm
and instead uses the TwoOperandAliasConstraint field in
the ArithLogicI instruction class.
This way all instructions that inherit ArithLogicI class
have the same macro defined.
The usage examples are added to test files.
Patch by Vladimir Medic
Modified:
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Mips/mips-alu-instructions.s
llvm/trunk/test/MC/Mips/mips64-alu-instructions.s
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=182048&r1=182047&r2=182048&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu May 16 15:24:27 2013
@@ -391,6 +391,7 @@ class ArithLogicI<string opstr, Operand
[(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
IIAlu, FrmI, opstr> {
let isReMaterializable = 1;
+ let TwoOperandAliasConstraint = "$rs = $rt";
}
// Arithmetic Multiply ADD/SUB
@@ -1098,8 +1099,6 @@ def : InstAlias<"mfc2 $rt, $rd",
(MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>;
def : InstAlias<"mtc2 $rt, $rd",
(MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>;
-def : InstAlias<"addiu $rs, $imm",
- (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rs, simm16:$imm), 0>;
def : InstAlias<"bnez $rs,$offset",
(BNE CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>,
Requires<[NotMips64]>;
Modified: llvm/trunk/test/MC/Mips/mips-alu-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips-alu-instructions.s?rev=182048&r1=182047&r2=182048&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips-alu-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/mips-alu-instructions.s Thu May 16 15:24:27 2013
@@ -7,6 +7,7 @@
# CHECK: and $9, $6, $7 # encoding: [0x24,0x48,0xc7,0x00]
# CHECK: andi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x30]
# CHECK: andi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x30]
+# CHECK: andi $9, $9, 17767 # encoding: [0x67,0x45,0x29,0x31]
# CHECK: clo $6, $7 # encoding: [0x21,0x30,0xe6,0x70]
# CHECK: clz $6, $7 # encoding: [0x20,0x30,0xe6,0x70]
# CHECK: ins $19, $9, 6, 7 # encoding: [0x84,0x61,0x33,0x7d]
@@ -14,6 +15,7 @@
# CHECK: or $3, $3, $5 # encoding: [0x25,0x18,0x65,0x00]
# CHECK: ori $4, $5, 17767 # encoding: [0x67,0x45,0xa4,0x34]
# CHECK: ori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x34]
+# CHECK: ori $11, $11, 128 # encoding: [0x80,0x00,0x6b,0x35]
# CHECK: rotr $9, $6, 7 # encoding: [0xc2,0x49,0x26,0x00]
# CHECK: rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00]
# CHECK: sll $4, $3, 7 # encoding: [0xc0,0x21,0x03,0x00]
@@ -28,13 +30,15 @@
# CHECK: srl $4, $3, 7 # encoding: [0xc2,0x21,0x03,0x00]
# CHECK: srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00]
# CHECK: xor $3, $3, $5 # encoding: [0x26,0x18,0x65,0x00]
-# CHECK: xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38]
# CHECK: xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38]
+# CHECK: xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38]
+# CHECK: xori $11, $11, 12 # encoding: [0x0c,0x00,0x6b,0x39]
# CHECK: wsbh $6, $7 # encoding: [0xa0,0x30,0x07,0x7c]
# CHECK: not $7, $8 # encoding: [0x27,0x38,0x00,0x01]
and $9, $6, $7
and $9, $6, 17767
andi $9, $6, 17767
+ andi $9, 17767
clo $6, $7
clz $6, $7
ins $19, $9, 6,7
@@ -42,6 +46,7 @@
or $3, $3, $5
or $4, $5, 17767
ori $9, $6, 17767
+ ori $11, 128
rotr $9, $6, 7
rotrv $9, $6, $7
sll $4, $3, 7
@@ -58,6 +63,7 @@
xor $3, $3, $5
xor $9, $6, 17767
xori $9, $6, 17767
+ xori $11, 12
wsbh $6, $7
not $7 ,$8
@@ -69,6 +75,7 @@
# CHECK: addi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x20]
# CHECK: addiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x24]
# CHECK: addi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x20]
+# CHECK: addi $9, $9, 17767 # encoding: [0x67,0x45,0x29,0x21]
# CHECK: addiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x24]
# CHECK: addiu $11, $11, 40 # encoding: [0x28,0x00,0x6b,0x25]
# CHECK: addu $9, $6, $7 # encoding: [0x21,0x48,0xc7,0x00]
@@ -91,6 +98,7 @@
add $9,$6,17767
addu $9,$6,-15001
addi $9,$6,17767
+ addi $9,17767
addiu $9,$6,-15001
addiu $11,40
addu $9,$6,$7
Modified: llvm/trunk/test/MC/Mips/mips64-alu-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64-alu-instructions.s?rev=182048&r1=182047&r2=182048&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64-alu-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/mips64-alu-instructions.s Thu May 16 15:24:27 2013
@@ -69,7 +69,9 @@
# CHECK: daddi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x60]
# CHECK: daddiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x64]
# CHECK: daddi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x60]
+# CHECK: daddi $9, $9, 17767 # encoding: [0x67,0x45,0x29,0x61]
# CHECK: daddiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x64]
+# CHECK: daddiu $9, $9, -15001 # encoding: [0x67,0xc5,0x29,0x65]
# CHECK: daddu $9, $6, $7 # encoding: [0x2d,0x48,0xc7,0x00]
# CHECK: madd $6, $7 # encoding: [0x00,0x00,0xc7,0x70]
# CHECK: maddu $6, $7 # encoding: [0x01,0x00,0xc7,0x70]
@@ -88,7 +90,9 @@
dadd $9,$6,17767
daddu $9,$6,-15001
daddi $9,$6,17767
+ daddi $9,17767
daddiu $9,$6,-15001
+ daddiu $9,-15001
daddu $9,$6,$7
madd $6,$7
maddu $6,$7
More information about the llvm-commits
mailing list