[llvm] r181894 - [PowerPC] Remove need for adjustFixupOffst hack
Ulrich Weigand
ulrich.weigand at de.ibm.com
Wed May 15 08:07:06 PDT 2013
Author: uweigand
Date: Wed May 15 10:07:06 2013
New Revision: 181894
URL: http://llvm.org/viewvc/llvm-project?rev=181894&view=rev
Log:
[PowerPC] Remove need for adjustFixupOffst hack
Now that applyFixup understands differently-sized fixups, we can define
fixup_ppc_lo16/fixup_ppc_lo16_ds/fixup_ppc_ha16 to properly be 2-byte
fixups, applied at an offset of 2 relative to the start of the
instruction text.
This has the benefit that if we actually need to generate a real
relocation record, its address will come out correctly automatically,
without having to fiddle with the offset in adjustFixupOffset.
Tested on both 64-bit and 32-bit PowerPC, using external and
integrated assembler.
Modified:
llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
llvm/trunk/test/MC/PowerPC/ppc64-fixups.s
Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp?rev=181894&r1=181893&r2=181894&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp Wed May 15 10:07:06 2013
@@ -57,13 +57,13 @@ static unsigned getFixupKindNumBytes(uns
case FK_Data_1:
return 1;
case FK_Data_2:
+ case PPC::fixup_ppc_ha16:
+ case PPC::fixup_ppc_lo16:
+ case PPC::fixup_ppc_lo16_ds:
return 2;
case FK_Data_4:
case PPC::fixup_ppc_brcond14:
case PPC::fixup_ppc_br24:
- case PPC::fixup_ppc_ha16:
- case PPC::fixup_ppc_lo16:
- case PPC::fixup_ppc_lo16_ds:
return 4;
case FK_Data_8:
return 8;
@@ -100,9 +100,9 @@ public:
// name offset bits flags
{ "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_ppc_lo16", 16, 16, 0 },
- { "fixup_ppc_ha16", 16, 16, 0 },
- { "fixup_ppc_lo16_ds", 16, 14, 0 },
+ { "fixup_ppc_lo16", 0, 16, 0 },
+ { "fixup_ppc_ha16", 0, 16, 0 },
+ { "fixup_ppc_lo16_ds", 0, 14, 0 },
{ "fixup_ppc_tlsreg", 0, 0, 0 },
{ "fixup_ppc_nofixup", 0, 0, 0 }
};
Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp?rev=181894&r1=181893&r2=181894&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp Wed May 15 10:07:06 2013
@@ -33,7 +33,6 @@ namespace {
virtual const MCSymbol *undefinedExplicitRelSym(const MCValue &Target,
const MCFixup &Fixup,
bool IsPCRel) const;
- virtual void adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset);
virtual void sortRelocs(const MCAssembler &Asm,
std::vector<ELFRelocationEntry> &Relocs);
@@ -240,19 +239,6 @@ const MCSymbol *PPCELFObjectWriter::unde
return NULL;
}
-void PPCELFObjectWriter::
-adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset) {
- switch ((unsigned)Fixup.getKind()) {
- case PPC::fixup_ppc_ha16:
- case PPC::fixup_ppc_lo16:
- case PPC::fixup_ppc_lo16_ds:
- RelocOffset += 2;
- break;
- default:
- break;
- }
-}
-
// The standard sorter only sorts on the r_offset field, but PowerPC can
// have multiple relocations at the same offset. Sort secondarily on the
// relocation type to avoid nondeterminism.
Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp?rev=181894&r1=181893&r2=181894&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp Wed May 15 10:07:06 2013
@@ -142,7 +142,7 @@ unsigned PPCMCCodeEmitter::getHA16Encodi
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
// Add a fixup for the branch target.
- Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
+ Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_ha16));
return 0;
}
@@ -153,7 +153,7 @@ unsigned PPCMCCodeEmitter::getLO16Encodi
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
// Add a fixup for the branch target.
- Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
+ Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_lo16));
return 0;
}
@@ -170,7 +170,7 @@ unsigned PPCMCCodeEmitter::getMemRIEncod
return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;
// Add a fixup for the displacement field.
- Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
+ Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_lo16));
return RegBits;
}
@@ -188,7 +188,7 @@ unsigned PPCMCCodeEmitter::getMemRIXEnco
return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits;
// Add a fixup for the displacement field.
- Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
+ Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_lo16_ds));
return RegBits;
}
Modified: llvm/trunk/test/MC/PowerPC/ppc64-fixups.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/PowerPC/ppc64-fixups.s?rev=181894&r1=181893&r2=181894&view=diff
==============================================================================
--- llvm/trunk/test/MC/PowerPC/ppc64-fixups.s (original)
+++ llvm/trunk/test/MC/PowerPC/ppc64-fixups.s Wed May 15 10:07:06 2013
@@ -8,113 +8,113 @@
# FIXME: .TOC. at tocbase
# CHECK: li 3, target at l # encoding: [0x38,0x60,A,A]
-# CHECK-NEXT: # fixup A - offset: 0, value: target at l, kind: fixup_ppc_lo16
-# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_LO target 0x0
+# CHECK-NEXT: # fixup A - offset: 2, value: target at l, kind: fixup_ppc_lo16
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
li 3, target at l
# CHECK: addis 3, 3, target at ha # encoding: [0x3c,0x63,A,A]
-# CHECK-NEXT: # fixup A - offset: 0, value: target at ha, kind: fixup_ppc_ha16
-# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_HA target 0x0
+# CHECK-NEXT: # fixup A - offset: 2, value: target at ha, kind: fixup_ppc_ha16
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0
addis 3, 3, target at ha
# CHECK: lis 3, target at ha # encoding: [0x3c,0x60,A,A]
-# CHECK-NEXT: # fixup A - offset: 0, value: target at ha, kind: fixup_ppc_ha16
-# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_HA target 0x0
+# CHECK-NEXT: # fixup A - offset: 2, value: target at ha, kind: fixup_ppc_ha16
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0
lis 3, target at ha
# CHECK: addi 4, 3, target at l # encoding: [0x38,0x83,A,A]
-# CHECK-NEXT: # fixup A - offset: 0, value: target at l, kind: fixup_ppc_lo16
-# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_LO target 0x0
+# CHECK-NEXT: # fixup A - offset: 2, value: target at l, kind: fixup_ppc_lo16
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
addi 4, 3, target at l
# CHECK: lwz 1, target at l(3) # encoding: [0x80,0x23,A,A]
-# CHECK-NEXT: # fixup A - offset: 0, value: target at l, kind: fixup_ppc_lo16
-# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_LO target 0x0
+# CHECK-NEXT: # fixup A - offset: 2, value: target at l, kind: fixup_ppc_lo16
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
lwz 1, target at l(3)
# CHECK: ld 1, target at l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
-# CHECK-NEXT: # fixup A - offset: 0, value: target at l, kind: fixup_ppc_lo16_ds
-# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_LO_DS target 0x0
+# CHECK-NEXT: # fixup A - offset: 2, value: target at l, kind: fixup_ppc_lo16_ds
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO_DS target 0x0
ld 1, target at l(3)
# CHECK: ld 1, target at toc(2) # encoding: [0xe8,0x22,A,0bAAAAAA00]
-# CHECK-NEXT: # fixup A - offset: 0, value: target at toc, kind: fixup_ppc_lo16_ds
-# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_DS target 0x0
+# CHECK-NEXT: # fixup A - offset: 2, value: target at toc, kind: fixup_ppc_lo16_ds
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_DS target 0x0
ld 1, target at toc(2)
# CHECK: addis 3, 2, target at toc@ha # encoding: [0x3c,0x62,A,A]
-# CHECK-NEXT: # fixup A - offset: 0, value: target at toc@ha, kind: fixup_ppc_ha16
-# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA target 0x0
+# CHECK-NEXT: # fixup A - offset: 2, value: target at toc@ha, kind: fixup_ppc_ha16
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_HA target 0x0
addis 3, 2, target at toc@ha
# CHECK: addi 4, 3, target at toc@l # encoding: [0x38,0x83,A,A]
-# CHECK-NEXT: # fixup A - offset: 0, value: target at toc@l, kind: fixup_ppc_lo16
-# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO target 0x0
+# CHECK-NEXT: # fixup A - offset: 2, value: target at toc@l, kind: fixup_ppc_lo16
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0
addi 4, 3, target at toc@l
# CHECK: lwz 1, target at toc@l(3) # encoding: [0x80,0x23,A,A]
-# CHECK-NEXT: # fixup A - offset: 0, value: target at toc@l, kind: fixup_ppc_lo16
-# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO target 0x0
+# CHECK-NEXT: # fixup A - offset: 2, value: target at toc@l, kind: fixup_ppc_lo16
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0
lwz 1, target at toc@l(3)
# CHECK: ld 1, target at toc@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
-# CHECK-NEXT: # fixup A - offset: 0, value: target at toc@l, kind: fixup_ppc_lo16_ds
-# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS target 0x0
+# CHECK-NEXT: # fixup A - offset: 2, value: target at toc@l, kind: fixup_ppc_lo16_ds
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO_DS target 0x0
ld 1, target at toc@l(3)
# FIXME: @tls
# CHECK: addis 3, 2, target at tprel@ha # encoding: [0x3c,0x62,A,A]
-# CHECK-NEXT: # fixup A - offset: 0, value: target at tprel@ha, kind: fixup_ppc_ha16
-# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TPREL16_HA target 0x0
+# CHECK-NEXT: # fixup A - offset: 2, value: target at tprel@ha, kind: fixup_ppc_ha16
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HA target 0x0
addis 3, 2, target at tprel@ha
# CHECK: addi 3, 3, target at tprel@l # encoding: [0x38,0x63,A,A]
-# CHECK-NEXT: # fixup A - offset: 0, value: target at tprel@l, kind: fixup_ppc_lo16
-# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TPREL16_LO target 0x0
+# CHECK-NEXT: # fixup A - offset: 2, value: target at tprel@l, kind: fixup_ppc_lo16
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_LO target 0x0
addi 3, 3, target at tprel@l
# CHECK: addis 3, 2, target at dtprel@ha # encoding: [0x3c,0x62,A,A]
-# CHECK-NEXT: # fixup A - offset: 0, value: target at dtprel@ha, kind: fixup_ppc_ha16
-# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_DTPREL16_HA target 0x0
+# CHECK-NEXT: # fixup A - offset: 2, value: target at dtprel@ha, kind: fixup_ppc_ha16
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HA target 0x0
addis 3, 2, target at dtprel@ha
# CHECK: addi 3, 3, target at dtprel@l # encoding: [0x38,0x63,A,A]
-# CHECK-NEXT: # fixup A - offset: 0, value: target at dtprel@l, kind: fixup_ppc_lo16
-# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_DTPREL16_LO target 0x0
+# CHECK-NEXT: # fixup A - offset: 2, value: target at dtprel@l, kind: fixup_ppc_lo16
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_LO target 0x0
addi 3, 3, target at dtprel@l
# CHECK: addis 3, 2, target at got@tprel at ha # encoding: [0x3c,0x62,A,A]
-# CHECK-NEXT: # fixup A - offset: 0, value: target at got@tprel at ha, kind: fixup_ppc_ha16
-# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_HA target 0x0
+# CHECK-NEXT: # fixup A - offset: 2, value: target at got@tprel at ha, kind: fixup_ppc_ha16
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_HA target 0x0
addis 3, 2, target at got@tprel at ha
# CHECK: ld 1, target at got@tprel at l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
-# CHECK-NEXT: # fixup A - offset: 0, value: target at got@tprel at l, kind: fixup_ppc_lo16_ds
-# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_LO_DS target 0x0
+# CHECK-NEXT: # fixup A - offset: 2, value: target at got@tprel at l, kind: fixup_ppc_lo16_ds
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_LO_DS target 0x0
ld 1, target at got@tprel at l(3)
# CHECK: addis 3, 2, target at got@tlsgd at ha # encoding: [0x3c,0x62,A,A]
-# CHECK-NEXT: # fixup A - offset: 0, value: target at got@tlsgd at ha, kind: fixup_ppc_ha16
-# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_HA target 0x0
+# CHECK-NEXT: # fixup A - offset: 2, value: target at got@tlsgd at ha, kind: fixup_ppc_ha16
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_HA target 0x0
addis 3, 2, target at got@tlsgd at ha
# CHECK: addi 3, 3, target at got@tlsgd at l # encoding: [0x38,0x63,A,A]
-# CHECK-NEXT: # fixup A - offset: 0, value: target at got@tlsgd at l, kind: fixup_ppc_lo16
-# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_LO target 0x0
+# CHECK-NEXT: # fixup A - offset: 2, value: target at got@tlsgd at l, kind: fixup_ppc_lo16
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_LO target 0x0
addi 3, 3, target at got@tlsgd at l
# CHECK: addis 3, 2, target at got@tlsld at ha # encoding: [0x3c,0x62,A,A]
-# CHECK-NEXT: # fixup A - offset: 0, value: target at got@tlsld at ha, kind: fixup_ppc_ha16
-# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_HA target 0x0
+# CHECK-NEXT: # fixup A - offset: 2, value: target at got@tlsld at ha, kind: fixup_ppc_ha16
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_HA target 0x0
addis 3, 2, target at got@tlsld at ha
# CHECK: addi 3, 3, target at got@tlsld at l # encoding: [0x38,0x63,A,A]
-# CHECK-NEXT: # fixup A - offset: 0, value: target at got@tlsld at l, kind: fixup_ppc_lo16
-# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_LO target 0x0
+# CHECK-NEXT: # fixup A - offset: 2, value: target at got@tlsld at l, kind: fixup_ppc_lo16
+# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_LO target 0x0
addi 3, 3, target at got@tlsld at l
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