[Mesa-dev] [PATCH 2/2] R600: Fix encoding for R600 family GPUs

[Vincent Lejeune]

Thank for fixing this !
Both patches are reviewed-by: vljn at ovi.com




----- Mail original -----
> De : Tom Stellard <tom at stellard.net>
> À : llvm-commits at cs.uiuc.edu
> Cc : mesa-dev at lists.freedesktop.org; Tom Stellard <thomas.stellard at amd.com>
> Envoyé le : Mercredi 15 mai 2013 1h03
> Objet : [Mesa-dev] [PATCH 2/2] R600: Fix encoding for R600 family GPUs
> 
> From: Tom Stellard <thomas.stellard at amd.com>
> 
> https://bugs.freedesktop.org/show_bug.cgi?id=64193
> https://bugs.freedesktop.org/show_bug.cgi?id=64257
> https://bugs.freedesktop.org/show_bug.cgi?id=64320
> 
> NOTE: This is a candidate for the 3.3 branch.
> ---
> lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp |  7 +++++++
> test/CodeGen/R600/r600-encoding.ll                 | 24 ++++++++++++++++++++++
> 2 files changed, 31 insertions(+)
> create mode 100644 test/CodeGen/R600/r600-encoding.ll
> 
> diff --git a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp 
> b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
> index c5bd01a..cb4cf0c 100644
> --- a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
> +++ b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
> @@ -179,6 +179,13 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst 
> &MI, raw_ostream &OS,
>      Emit((u_int32_t) 0, OS);
>    } else {
>      uint64_t Inst = getBinaryCodeForInstr(MI, Fixups);
> +    if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&
> +       ((Desc.TSFlags & R600_InstFlag::OP1) ||
> +         Desc.TSFlags & R600_InstFlag::OP2)) {
> +      uint64_t ISAOpCode = Inst & (0x3FFULL << 39);
> +      Inst &= ~(0x3FFULL << 39);
> +      Inst |= ISAOpCode << 1;
> +    }
>      Emit(Inst, OS);
>    }
> }
> diff --git a/test/CodeGen/R600/r600-encoding.ll 
> b/test/CodeGen/R600/r600-encoding.ll
> new file mode 100644
> index 0000000..c8040a1
> --- /dev/null
> +++ b/test/CodeGen/R600/r600-encoding.ll
> @@ -0,0 +1,24 @@
> +; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=redwood | FileCheck 
> --check-prefix=EG-CHECK %s
> +; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rs880 | FileCheck 
> --check-prefix=R600-CHECK %s
> +
> +; The earliest R600 GPUs have a slightly different encoding than the rest of
> +; the VLIW4/5 GPUs.
> +
> +; EG-CHECK: @test
> +; EG-CHECK: MUL_IEEE {{[ *TXYZW.,0-9]+}} ; encoding: 
> [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x01,0x[0-9a-f]+,0x[0-9a-f]+}}]
> +
> +; R600-CHECK: @test
> +; R600-CHECK: MUL_IEEE {{[ *TXYZW.,0-9]+}} ; encoding: 
> [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x02,0x[0-9a-f]+,0x[0-9a-f]+}}]
> +
> +define void @test() {
> +entry:
> +  %0 = call float @llvm.R600.load.input(i32 0)
> +  %1 = call float @llvm.R600.load.input(i32 1)
> +  %2 = fmul float %0, %1
> +  call void @llvm.AMDGPU.store.output(float %2, i32 0)
> +  ret void
> +}
> +
> +declare float @llvm.R600.load.input(i32) readnone
> +
> +declare void @llvm.AMDGPU.store.output(float, i32)
> -- 
> 1.7.11.4
> 
> _______________________________________________
> mesa-dev mailing list
> mesa-dev at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
>