[llvm] r181771 - [SystemZ] Match operands to fields by name rather than by order

[Jakob Stoklund Olesen]

On May 14, 2013, at 2:36 AM, Richard Sandiford <rsandifo at linux.vnet.ibm.com> wrote:

> +
> +  // Maps of asm register numbers to LLVM register numbers, with 0 indicating
> +  // an invalid register.  We don't use the register classes directly because
> +  // they specify the allocation order.
> +  extern const unsigned GR32Regs[16];
> +  extern const unsigned GR64Regs[16];
> +  extern const unsigned GR128Regs[16];
> +  extern const unsigned FP32Regs[16];
> +  extern const unsigned FP64Regs[16];
> +  extern const unsigned FP128Regs[16];
> }

This shouldn’t be necessary. Callee saved registers are automatically moved to the end of the allocation order by the register allocator, and reserved registers are filtered out.

In more complicated cases, you can specify an alternative allocation order separate from the list of registers in the register class. See ARMRegisterInfo.td for AltOrders examples:

// Generic 128-bit vector register class.
def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
                        (sequence "Q%u", 0, 15)> {
  // Allocate non-VFP2 aliases Q8-Q15 first.
  let AltOrders = [(rotl QPR, 8)];
  let AltOrderSelect = [{ return 1; }];
}

This should make it easy to always have register classes laid out in encoding order.

/jakob