[llvm] r181801 - Fix ARM FastISel tests, as a first step to enabling ARM FastISel
Derek Schuff
dschuff at google.com
Tue May 14 09:26:39 PDT 2013
Author: dschuff
Date: Tue May 14 11:26:38 2013
New Revision: 181801
URL: http://llvm.org/viewvc/llvm-project?rev=181801&view=rev
Log:
Fix ARM FastISel tests, as a first step to enabling ARM FastISel
ARM FastISel is currently only enabled for iOS non-Thumb1, and I'm working on
enabling it for other targets. As a first step I've fixed some of the tests.
Changes to ARM FastISel tests:
- Different triples don't generate the same relocations (especially
movw/movt versus constant pool loads). Use a regex to allow either.
- Mangling is different. Use a regex to allow either.
- The reserved registers are sometimes different, so registers get
allocated in a different order. Capture the names only where this
occurs.
- Add -verify-machineinstrs to some tests where it works. It doesn't
work everywhere it should yet.
- Add -fast-isel-abort to many tests that didn't have it before.
- Split out the VarArg test from fast-isel-call.ll into its own
test. This simplifies test setup because of --check-prefix.
Patch by JF Bastien
Modified:
llvm/trunk/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll
llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll
llvm/trunk/test/CodeGen/ARM/fast-isel-call-multi-reg-return.ll
llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll
llvm/trunk/test/CodeGen/ARM/fast-isel-crash.ll
llvm/trunk/test/CodeGen/ARM/fast-isel-crash2.ll
llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll
llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll
llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll
llvm/trunk/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
llvm/trunk/test/CodeGen/ARM/fast-isel-mvn.ll
llvm/trunk/test/CodeGen/ARM/fast-isel-pic.ll
llvm/trunk/test/CodeGen/ARM/fast-isel-redefinition.ll
llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll
llvm/trunk/test/CodeGen/ARM/fast-isel-static.ll
llvm/trunk/test/CodeGen/ARM/fast-isel.ll
llvm/trunk/test/CodeGen/Thumb2/large-call.ll
llvm/trunk/test/MC/ARM/data-in-code.ll
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll?rev=181801&r1=181800&r2=181801&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll Tue May 14 11:26:38 2013
@@ -26,8 +26,8 @@ entry:
; THUMB: t2
%addr = alloca i32*, align 4
store i32* getelementptr inbounds ([3 x [3 x %struct.A]]* @A, i32 0, i32 2, i32 2, i32 3, i32 1, i32 2, i32 2), i32** %addr, align 4
-; ARM: movw r1, #1148
-; ARM: add r0, r0, r1
+; ARM: movw [[R:r[0-9]+]], #1148
+; ARM: add r0, r{{[0-9]+}}, [[R]]
; THUMB: addw r0, r0, #1148
%0 = load i32** %addr, align 4
ret i32* %0
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll?rev=181801&r1=181800&r2=181801&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll Tue May 14 11:26:38 2013
@@ -7,8 +7,8 @@ entry:
; ARM: t1:
%x = add i32 %a, %b
br i1 1, label %if.then, label %if.else
-; THUMB-NOT: b LBB0_1
-; ARM-NOT: b LBB0_1
+; THUMB-NOT: b {{\.?}}LBB0_1
+; ARM-NOT: b {{\.?}}LBB0_1
if.then: ; preds = %entry
call void @foo1()
@@ -16,8 +16,8 @@ if.then:
if.else: ; preds = %entry
br i1 0, label %if.then2, label %if.else3
-; THUMB: b LBB0_4
-; ARM: b LBB0_4
+; THUMB: b {{\.?}}LBB0_4
+; ARM: b {{\.?}}LBB0_4
if.then2: ; preds = %if.else
call void @foo2()
@@ -26,8 +26,8 @@ if.then2:
if.else3: ; preds = %if.else
%y = sub i32 %a, %b
br i1 1, label %if.then5, label %if.end
-; THUMB-NOT: b LBB0_5
-; ARM-NOT: b LBB0_5
+; THUMB-NOT: b {{\.?}}LBB0_5
+; ARM-NOT: b {{\.?}}LBB0_5
if.then5: ; preds = %if.else3
call void @foo1()
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-call-multi-reg-return.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-call-multi-reg-return.ll?rev=181801&r1=181800&r2=181801&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-call-multi-reg-return.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-call-multi-reg-return.ll Tue May 14 11:26:38 2013
@@ -1,5 +1,5 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
; Fast-isel can't handle non-double multi-reg retvals.
; This test just check to make sure we don't hit the assert in FinishCall.
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll?rev=181801&r1=181800&r2=181801&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll Tue May 14 11:26:38 2013
@@ -2,8 +2,12 @@
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=THUMB-LONG
-; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP
-; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=THUMB-NOVFP
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=THUMB-NOVFP
+
+; Note that some of these tests assume that relocations are either
+; movw/movt or constant pool loads. Different platforms will select
+; different approaches.
define i32 @t0(i1 zeroext %a) nounwind {
%1 = zext i1 %a to i32
@@ -88,53 +92,53 @@ declare zeroext i1 @t9();
define i32 @t10(i32 %argc, i8** nocapture %argv) {
entry:
; ARM: @t10
-; ARM: movw r0, #0
-; ARM: movw r1, #248
-; ARM: movw r2, #187
-; ARM: movw r3, #28
-; ARM: movw r9, #40
-; ARM: movw r12, #186
-; ARM: uxtb r0, r0
-; ARM: uxtb r1, r1
-; ARM: uxtb r2, r2
-; ARM: uxtb r3, r3
-; ARM: uxtb r9, r9
-; ARM: str r9, [sp]
-; ARM: uxtb r9, r12
-; ARM: str r9, [sp, #4]
-; ARM: bl _bar
+; ARM: movw [[R0:l?r[0-9]*]], #0
+; ARM: movw [[R1:l?r[0-9]*]], #248
+; ARM: movw [[R2:l?r[0-9]*]], #187
+; ARM: movw [[R3:l?r[0-9]*]], #28
+; ARM: movw [[R4:l?r[0-9]*]], #40
+; ARM: movw [[R5:l?r[0-9]*]], #186
+; ARM: uxtb [[R0]], [[R0]]
+; ARM: uxtb [[R1]], [[R1]]
+; ARM: uxtb [[R2]], [[R2]]
+; ARM: uxtb [[R3]], [[R3]]
+; ARM: uxtb [[R4]], [[R4]]
+; ARM: str [[R4]], [sp]
+; ARM: uxtb [[R4]], [[R5]]
+; ARM: str [[R4]], [sp, #4]
+; ARM: bl {{_?}}bar
; ARM-LONG: @t10
-; ARM-LONG: movw lr, :lower16:L_bar$non_lazy_ptr
-; ARM-LONG: movt lr, :upper16:L_bar$non_lazy_ptr
-; ARM-LONG: ldr lr, [lr]
-; ARM-LONG: blx lr
+; ARM-LONG: {{(movw)|(ldr)}} [[R:l?r[0-9]*]], {{(:lower16:L_bar\$non_lazy_ptr)|(.LCPI)}}
+; ARM-LONG: {{(movt [[R]], :upper16:L_bar\$non_lazy_ptr)?}}
+; ARM-LONG: ldr [[R]], {{\[}}[[R]]{{\]}}
+; ARM-LONG: blx [[R]]
; THUMB: @t10
-; THUMB: movs r0, #0
-; THUMB: movt r0, #0
-; THUMB: movs r1, #248
-; THUMB: movt r1, #0
-; THUMB: movs r2, #187
-; THUMB: movt r2, #0
-; THUMB: movs r3, #28
-; THUMB: movt r3, #0
-; THUMB: movw r9, #40
-; THUMB: movt r9, #0
-; THUMB: movw r12, #186
-; THUMB: movt r12, #0
-; THUMB: uxtb r0, r0
-; THUMB: uxtb r1, r1
-; THUMB: uxtb r2, r2
-; THUMB: uxtb r3, r3
-; THUMB: uxtb.w r9, r9
-; THUMB: str.w r9, [sp]
-; THUMB: uxtb.w r9, r12
-; THUMB: str.w r9, [sp, #4]
-; THUMB: bl _bar
+; THUMB: movs [[R0:l?r[0-9]*]], #0
+; THUMB: movt [[R0]], #0
+; THUMB: movs [[R1:l?r[0-9]*]], #248
+; THUMB: movt [[R1]], #0
+; THUMB: movs [[R2:l?r[0-9]*]], #187
+; THUMB: movt [[R2]], #0
+; THUMB: movs [[R3:l?r[0-9]*]], #28
+; THUMB: movt [[R3]], #0
+; THUMB: movw [[R4:l?r[0-9]*]], #40
+; THUMB: movt [[R4]], #0
+; THUMB: movw [[R5:l?r[0-9]*]], #186
+; THUMB: movt [[R5]], #0
+; THUMB: uxtb [[R0]], [[R0]]
+; THUMB: uxtb [[R1]], [[R1]]
+; THUMB: uxtb [[R2]], [[R2]]
+; THUMB: uxtb [[R3]], [[R3]]
+; THUMB: uxtb.w [[R4]], [[R4]]
+; THUMB: str.w [[R4]], [sp]
+; THUMB: uxtb.w [[R4]], [[R5]]
+; THUMB: str.w [[R4]], [sp, #4]
+; THUMB: bl {{_?}}bar
; THUMB-LONG: @t10
-; THUMB-LONG: movw lr, :lower16:L_bar$non_lazy_ptr
-; THUMB-LONG: movt lr, :upper16:L_bar$non_lazy_ptr
-; THUMB-LONG: ldr.w lr, [lr]
-; THUMB-LONG: blx lr
+; THUMB-LONG: {{(movw)|(ldr.n)}} [[R:l?r[0-9]*]], {{(:lower16:L_bar\$non_lazy_ptr)|(.LCPI)}}
+; THUMB-LONG: {{(movt [[R]], :upper16:L_bar\$non_lazy_ptr)?}}
+; THUMB-LONG: ldr{{(.w)?}} [[R]], {{\[}}[[R]]{{\]}}
+; THUMB-LONG: blx [[R]]
%call = call i32 @bar(i8 zeroext 0, i8 zeroext -8, i8 zeroext -69, i8 zeroext 28, i8 zeroext 40, i8 zeroext -70)
ret i32 0
}
@@ -147,12 +151,12 @@ define i32 @bar0(i32 %i) nounwind {
define void @foo3() uwtable {
; ARM: movw r0, #0
-; ARM: movw r1, :lower16:_bar0
-; ARM: movt r1, :upper16:_bar0
+; ARM: {{(movw r1, :lower16:_?bar0)|(ldr r1, .LCPI)}}
+; ARM: {{(movt r1, :upper16:_?bar0)|(ldr r1, \[r1\])}}
; ARM: blx r1
; THUMB: movs r0, #0
-; THUMB: movw r1, :lower16:_bar0
-; THUMB: movt r1, :upper16:_bar0
+; THUMB: {{(movw r1, :lower16:_?bar0)|(ldr.n r1, .LCPI)}}
+; THUMB: {{(movt r1, :upper16:_?bar0)|(ldr r1, \[r1\])}}
; THUMB: blx r1
%fptr = alloca i32 (i32)*, align 8
store i32 (i32)* @bar0, i32 (i32)** %fptr, align 8
@@ -164,66 +168,23 @@ define void @foo3() uwtable {
define i32 @LibCall(i32 %a, i32 %b) {
entry:
; ARM: LibCall
-; ARM: bl ___udivsi3
+; ARM: bl {{___udivsi3|__aeabi_uidiv}}
; ARM-LONG: LibCall
-; ARM-LONG: movw r2, :lower16:L___udivsi3$non_lazy_ptr
-; ARM-LONG: movt r2, :upper16:L___udivsi3$non_lazy_ptr
+; ARM-LONG: {{(movw r2, :lower16:L___udivsi3\$non_lazy_ptr)|(ldr r2, .LCPI)}}
+; ARM-LONG: {{(movt r2, :upper16:L___udivsi3\$non_lazy_ptr)?}}
; ARM-LONG: ldr r2, [r2]
; ARM-LONG: blx r2
; THUMB: LibCall
-; THUMB: bl ___udivsi3
+; THUMB: bl {{___udivsi3|__aeabi_uidiv}}
; THUMB-LONG: LibCall
-; THUMB-LONG: movw r2, :lower16:L___udivsi3$non_lazy_ptr
-; THUMB-LONG: movt r2, :upper16:L___udivsi3$non_lazy_ptr
+; THUMB-LONG: {{(movw r2, :lower16:L___udivsi3\$non_lazy_ptr)|(ldr.n r2, .LCPI)}}
+; THUMB-LONG: {{(movt r2, :upper16:L___udivsi3\$non_lazy_ptr)?}}
; THUMB-LONG: ldr r2, [r2]
; THUMB-LONG: blx r2
%tmp1 = udiv i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
}
-define i32 @VarArg() nounwind {
-entry:
- %i = alloca i32, align 4
- %j = alloca i32, align 4
- %k = alloca i32, align 4
- %m = alloca i32, align 4
- %n = alloca i32, align 4
- %tmp = alloca i32, align 4
- %0 = load i32* %i, align 4
- %1 = load i32* %j, align 4
- %2 = load i32* %k, align 4
- %3 = load i32* %m, align 4
- %4 = load i32* %n, align 4
-; ARM: VarArg
-; ARM: mov r7, sp
-; ARM: movw r0, #5
-; ARM: ldr r1, [r7, #-4]
-; ARM: ldr r2, [r7, #-8]
-; ARM: ldr r3, [r7, #-12]
-; ARM: ldr r9, [sp, #16]
-; ARM: ldr r12, [sp, #12]
-; ARM: str r9, [sp]
-; ARM: str r12, [sp, #4]
-; ARM: bl _CallVariadic
-; THUMB: mov r7, sp
-; THUMB: movs r0, #5
-; THUMB: movt r0, #0
-; THUMB: ldr r1, [sp, #28]
-; THUMB: ldr r2, [sp, #24]
-; THUMB: ldr r3, [sp, #20]
-; THUMB: ldr.w r9, [sp, #16]
-; THUMB: ldr.w r12, [sp, #12]
-; THUMB: str.w r9, [sp]
-; THUMB: str.w r12, [sp, #4]
-; THUMB: bl _CallVariadic
- %call = call i32 (i32, ...)* @CallVariadic(i32 5, i32 %0, i32 %1, i32 %2, i32 %3, i32 %4)
- store i32 %call, i32* %tmp, align 4
- %5 = load i32* %tmp, align 4
- ret i32 %5
-}
-
-declare i32 @CallVariadic(i32, ...)
-
; Test fastcc
define fastcc void @fast_callee(float %i) ssp {
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-crash.ll?rev=181801&r1=181800&r2=181801&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-crash.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-crash.ll Tue May 14 11:26:38 2013
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=thumbv7-apple-darwin
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-apple-darwin
%union.anon = type { <16 x i32> }
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-crash2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-crash2.ll?rev=181801&r1=181800&r2=181801&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-crash2.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-crash2.ll Tue May 14 11:26:38 2013
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=thumbv7-apple-darwin
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-apple-darwin
; rdar://9515076
; (Make sure this doesn't crash.)
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll?rev=181801&r1=181800&r2=181801&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-deadcode.ll Tue May 14 11:26:38 2013
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
; Target-specific selector can't properly handle the double because it isn't
; being passed via a register, so the materialized arguments become dead code.
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll?rev=181801&r1=181800&r2=181801&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll Tue May 14 11:26:38 2013
@@ -3,33 +3,37 @@
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=THUMB-LONG
+; Note that some of these tests assume that relocations are either
+; movw/movt or constant pool loads. Different platforms will select
+; different approaches.
+
@message1 = global [60 x i8] c"The LLVM Compiler Infrastructure\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 1
@temp = common global [60 x i8] zeroinitializer, align 1
define void @t1() nounwind ssp {
; ARM: t1
-; ARM: movw r0, :lower16:_message1
-; ARM: movt r0, :upper16:_message1
+; ARM: {{(movw r0, :lower16:_?message1)|(ldr r0, .LCPI)}}
+; ARM: {{(movt r0, :upper16:_?message1)|(ldr r0, \[r0\])}}
; ARM: add r0, r0, #5
; ARM: movw r1, #64
; ARM: movw r2, #10
; ARM: uxtb r1, r1
-; ARM: bl _memset
+; ARM: bl {{_?}}memset
; ARM-LONG: t1
; ARM-LONG: movw r3, :lower16:L_memset$non_lazy_ptr
; ARM-LONG: movt r3, :upper16:L_memset$non_lazy_ptr
; ARM-LONG: ldr r3, [r3]
; ARM-LONG: blx r3
; THUMB: t1
-; THUMB: movw r0, :lower16:_message1
-; THUMB: movt r0, :upper16:_message1
+; THUMB: {{(movw r0, :lower16:_?message1)|(ldr.n r0, .LCPI)}}
+; THUMB: {{(movt r0, :upper16:_?message1)|(ldr r0, \[r0\])}}
; THUMB: adds r0, #5
; THUMB: movs r1, #64
; THUMB: movt r1, #0
; THUMB: movs r2, #10
; THUMB: movt r2, #0
; THUMB: uxtb r1, r1
-; THUMB: bl _memset
+; THUMB: bl {{_?}}memset
; THUMB-LONG: t1
; THUMB-LONG: movw r3, :lower16:L_memset$non_lazy_ptr
; THUMB-LONG: movt r3, :upper16:L_memset$non_lazy_ptr
@@ -43,31 +47,33 @@ declare void @llvm.memset.p0i8.i32(i8* n
define void @t2() nounwind ssp {
; ARM: t2
-; ARM: movw r0, :lower16:L_temp$non_lazy_ptr
-; ARM: movt r0, :upper16:L_temp$non_lazy_ptr
+; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
+; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; ARM: ldr r0, [r0]
; ARM: add r1, r0, #4
; ARM: add r0, r0, #16
; ARM: movw r2, #17
-; ARM: str r0, [sp] @ 4-byte Spill
+; ARM: str r0, [sp[[SLOT:[, #0-9]*]]] @ 4-byte Spill
; ARM: mov r0, r1
-; ARM: ldr r1, [sp] @ 4-byte Reload
-; ARM: bl _memcpy
+; ARM: ldr r1, [sp[[SLOT]]] @ 4-byte Reload
+; ARM: bl {{_?}}memcpy
; ARM-LONG: t2
; ARM-LONG: movw r3, :lower16:L_memcpy$non_lazy_ptr
; ARM-LONG: movt r3, :upper16:L_memcpy$non_lazy_ptr
; ARM-LONG: ldr r3, [r3]
; ARM-LONG: blx r3
; THUMB: t2
-; THUMB: movw r0, :lower16:L_temp$non_lazy_ptr
-; THUMB: movt r0, :upper16:L_temp$non_lazy_ptr
+; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
+; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; THUMB: ldr r0, [r0]
; THUMB: adds r1, r0, #4
; THUMB: adds r0, #16
; THUMB: movs r2, #17
; THUMB: movt r2, #0
+; THUMB: str r0, [sp[[SLOT:[, #0-9]*]]] @ 4-byte Spill
; THUMB: mov r0, r1
-; THUMB: bl _memcpy
+; THUMB: ldr r1, [sp[[SLOT]]] @ 4-byte Reload
+; THUMB: bl {{_?}}memcpy
; THUMB-LONG: t2
; THUMB-LONG: movw r3, :lower16:L_memcpy$non_lazy_ptr
; THUMB-LONG: movt r3, :upper16:L_memcpy$non_lazy_ptr
@@ -81,29 +87,31 @@ declare void @llvm.memcpy.p0i8.p0i8.i32(
define void @t3() nounwind ssp {
; ARM: t3
-; ARM: movw r0, :lower16:L_temp$non_lazy_ptr
-; ARM: movt r0, :upper16:L_temp$non_lazy_ptr
+; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
+; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; ARM: ldr r0, [r0]
; ARM: add r1, r0, #4
; ARM: add r0, r0, #16
; ARM: movw r2, #10
; ARM: mov r0, r1
-; ARM: bl _memmove
+; ARM: bl {{_?}}memmove
; ARM-LONG: t3
; ARM-LONG: movw r3, :lower16:L_memmove$non_lazy_ptr
; ARM-LONG: movt r3, :upper16:L_memmove$non_lazy_ptr
; ARM-LONG: ldr r3, [r3]
; ARM-LONG: blx r3
; THUMB: t3
-; THUMB: movw r0, :lower16:L_temp$non_lazy_ptr
-; THUMB: movt r0, :upper16:L_temp$non_lazy_ptr
+; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
+; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; THUMB: ldr r0, [r0]
; THUMB: adds r1, r0, #4
; THUMB: adds r0, #16
; THUMB: movs r2, #10
; THUMB: movt r2, #0
+; THUMB: str r0, [sp[[SLOT:[, #0-9]*]]] @ 4-byte Spill
; THUMB: mov r0, r1
-; THUMB: bl _memmove
+; THUMB: ldr r1, [sp[[SLOT]]] @ 4-byte Reload
+; THUMB: bl {{_?}}memmove
; THUMB-LONG: t3
; THUMB-LONG: movw r3, :lower16:L_memmove$non_lazy_ptr
; THUMB-LONG: movt r3, :upper16:L_memmove$non_lazy_ptr
@@ -115,8 +123,8 @@ define void @t3() nounwind ssp {
define void @t4() nounwind ssp {
; ARM: t4
-; ARM: movw r0, :lower16:L_temp$non_lazy_ptr
-; ARM: movt r0, :upper16:L_temp$non_lazy_ptr
+; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
+; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; ARM: ldr r0, [r0]
; ARM: ldr r1, [r0, #16]
; ARM: str r1, [r0, #4]
@@ -126,8 +134,8 @@ define void @t4() nounwind ssp {
; ARM: strh r1, [r0, #12]
; ARM: bx lr
; THUMB: t4
-; THUMB: movw r0, :lower16:L_temp$non_lazy_ptr
-; THUMB: movt r0, :upper16:L_temp$non_lazy_ptr
+; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
+; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; THUMB: ldr r0, [r0]
; THUMB: ldr r1, [r0, #16]
; THUMB: str r1, [r0, #4]
@@ -144,8 +152,8 @@ declare void @llvm.memmove.p0i8.p0i8.i32
define void @t5() nounwind ssp {
; ARM: t5
-; ARM: movw r0, :lower16:L_temp$non_lazy_ptr
-; ARM: movt r0, :upper16:L_temp$non_lazy_ptr
+; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
+; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; ARM: ldr r0, [r0]
; ARM: ldrh r1, [r0, #16]
; ARM: strh r1, [r0, #4]
@@ -159,8 +167,8 @@ define void @t5() nounwind ssp {
; ARM: strh r1, [r0, #12]
; ARM: bx lr
; THUMB: t5
-; THUMB: movw r0, :lower16:L_temp$non_lazy_ptr
-; THUMB: movt r0, :upper16:L_temp$non_lazy_ptr
+; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
+; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; THUMB: ldr r0, [r0]
; THUMB: ldrh r1, [r0, #16]
; THUMB: strh r1, [r0, #4]
@@ -179,8 +187,8 @@ define void @t5() nounwind ssp {
define void @t6() nounwind ssp {
; ARM: t6
-; ARM: movw r0, :lower16:L_temp$non_lazy_ptr
-; ARM: movt r0, :upper16:L_temp$non_lazy_ptr
+; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
+; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; ARM: ldr r0, [r0]
; ARM: ldrb r1, [r0, #16]
; ARM: strb r1, [r0, #4]
@@ -204,8 +212,8 @@ define void @t6() nounwind ssp {
; ARM: strb r1, [r0, #13]
; ARM: bx lr
; THUMB: t6
-; THUMB: movw r0, :lower16:L_temp$non_lazy_ptr
-; THUMB: movt r0, :upper16:L_temp$non_lazy_ptr
+; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
+; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; THUMB: ldr r0, [r0]
; THUMB: ldrb r1, [r0, #16]
; THUMB: strb r1, [r0, #4]
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll?rev=181801&r1=181800&r2=181801&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll Tue May 14 11:26:38 2013
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=ARM
define i32 @t1(i32* nocapture %ptr) nounwind readonly {
entry:
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll?rev=181801&r1=181800&r2=181801&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll Tue May 14 11:26:38 2013
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
; rdar://10418009
define zeroext i16 @t1(i16* nocapture %a) nounwind uwtable readonly ssp {
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-mvn.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-mvn.ll?rev=181801&r1=181800&r2=181801&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-mvn.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-mvn.ll Tue May 14 11:26:38 2013
@@ -1,5 +1,5 @@
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
; rdar://10412592
; Note: The Thumb code is being generated by the target-independent selector.
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-pic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-pic.ll?rev=181801&r1=181800&r2=181801&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-pic.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-pic.ll Tue May 14 11:26:38 2013
@@ -1,7 +1,7 @@
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=arm-apple-ios | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s --check-prefix=THUMB-ELF
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=arm-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s --check-prefix=THUMB-ELF
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefix=ARMv7-ELF
@g = global i32 0, align 4
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-redefinition.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-redefinition.ll?rev=181801&r1=181800&r2=181801&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-redefinition.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-redefinition.ll Tue May 14 11:26:38 2013
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -verify-machineinstrs -optimize-regalloc -regalloc=basic < %s
+; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -optimize-regalloc -regalloc=basic < %s
; This isn't exactly a useful set of command-line options, but check that it
; doesn't crash. (It was crashing because a register was getting redefined.)
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll?rev=181801&r1=181800&r2=181801&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll Tue May 14 11:26:38 2013
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
define i32 @t1(i1 %c) nounwind readnone {
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-static.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-static.ll?rev=181801&r1=181800&r2=181801&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-static.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-static.ll Tue May 14 11:26:38 2013
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -verify-machineinstrs -relocation-model=static -arm-long-calls | FileCheck -check-prefix=LONG %s
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -verify-machineinstrs -relocation-model=static | FileCheck -check-prefix=NORM %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static -arm-long-calls | FileCheck -check-prefix=LONG %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static | FileCheck -check-prefix=NORM %s
define void @myadd(float* %sum, float* %addend) nounwind {
entry:
@@ -24,7 +24,7 @@ entry:
store float 0.000000e+00, float* %ztot, align 4
store float 1.000000e+00, float* %z, align 4
; CHECK-LONG: blx r
-; CHECK-NORM: bl _myadd
+; CHECK-NORM: bl {{_?}}myadd
call void @myadd(float* %ztot, float* %z)
ret i32 0
}
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel.ll?rev=181801&r1=181800&r2=181801&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel.ll Tue May 14 11:26:38 2013
@@ -144,15 +144,19 @@ define void @test4() {
store i32 %b, i32* @test4g
ret void
-; THUMB: movw r0, :lower16:L_test4g$non_lazy_ptr
-; THUMB: movt r0, :upper16:L_test4g$non_lazy_ptr
+
+; Note that relocations are either movw/movt or constant pool
+; loads. Different platforms will select different approaches.
+
+; THUMB: {{(movw r0, :lower16:L_test4g\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
+; THUMB: {{(movt r0, :upper16:L_test4g\$non_lazy_ptr)?}}
; THUMB: ldr r0, [r0]
; THUMB: ldr r1, [r0]
; THUMB: adds r1, #1
; THUMB: str r1, [r0]
-; ARM: movw r0, :lower16:L_test4g$non_lazy_ptr
-; ARM: movt r0, :upper16:L_test4g$non_lazy_ptr
+; ARM: {{(movw r0, :lower16:L_test4g\$non_lazy_ptr)|(ldr r0, .LCPI)}}
+; ARM: {{(movt r0, :upper16:L_test4g\$non_lazy_ptr)?}}
; ARM: ldr r0, [r0]
; ARM: ldr r1, [r0]
; ARM: add r1, r1, #1
Modified: llvm/trunk/test/CodeGen/Thumb2/large-call.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/large-call.ll?rev=181801&r1=181800&r2=181801&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/large-call.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/large-call.ll Tue May 14 11:26:38 2013
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -mcpu=cortex-a8 | FileCheck %s
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mcpu=cortex-a8 | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
target triple = "thumbv7-apple-ios0.0.0"
Modified: llvm/trunk/test/MC/ARM/data-in-code.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/data-in-code.ll?rev=181801&r1=181800&r2=181801&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/data-in-code.ll (original)
+++ llvm/trunk/test/MC/ARM/data-in-code.ll Tue May 14 11:26:38 2013
@@ -1,7 +1,9 @@
-;; RUN: llc -O0 -mtriple=armv7-linux-gnueabi -filetype=obj %s -o - | \
+;; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort \
+;; RUN: -mtriple=armv7-linux-gnueabi -filetype=obj %s -o - | \
;; RUN: llvm-readobj -t | FileCheck -check-prefix=ARM %s
-;; RUN: llc -O0 -mtriple=thumbv7-linux-gnueabi -filetype=obj %s -o - | \
+;; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort \
+;; RUN: -mtriple=thumbv7-linux-gnueabi -filetype=obj %s -o - | \
;; RUN: llvm-readobj -t | FileCheck -check-prefix=TMB %s
;; Ensure that if a jump table is generated that it has Mapping Symbols
@@ -119,7 +121,7 @@ exit:
;; ARM: Symbol {
;; ARM: Name: $a
-;; ARM-NEXT: Value: 0xAC
+;; ARM-NEXT: Value: 0x{{[0-9A-F]+}}
;; ARM-NEXT: Size: 0
;; ARM-NEXT: Binding: Local
;; ARM-NEXT: Type: None
@@ -135,7 +137,7 @@ exit:
;; ARM: Symbol {
;; ARM: Name: $d
-;; ARM-NEXT: Value: 0x30
+;; ARM-NEXT: Value: 0x{{[0-9A-F]+}}
;; ARM-NEXT: Size: 0
;; ARM-NEXT: Binding: Local
;; ARM-NEXT: Type: None
@@ -146,7 +148,7 @@ exit:
;; TMB: Symbol {
;; TMB: Name: $d.2
-;; TMB-NEXT: Value: 0x16
+;; TMB-NEXT: Value: 0x{{[0-9A-F]+}}
;; TMB-NEXT: Size: 0
;; TMB-NEXT: Binding: Local
;; TMB-NEXT: Type: None
@@ -164,7 +166,7 @@ exit:
;; TMB: Symbol {
;; TMB: Name: $t
-;; TMB-NEXT: Value: 0x36
+;; TMB-NEXT: Value: 0x{{[0-9A-F]+}}
;; TMB-NEXT: Size: 0
;; TMB-NEXT: Binding: Local
;; TMB-NEXT: Type: None
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