[llvm] r181729 - Mips assembler: Assembler macro ADDIU $rs,imm

[Jack Carter]

Tim,

This looks like something we can use. 

  /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a
  /// two-operand matcher inst-alias for a three operand instruction.
  /// For example, the arm instruction "add r3, r3, r5" can be written
  /// as "add r3, r5". The constraint is of the same form as a tied-operand
  /// constraint. For example, "$Rn = $Rd".

Thanks for the pointer,

Jack
________________________________________
From: Tim Northover [t.p.northover at gmail.com]
Sent: Monday, May 13, 2013 2:02 PM
To: Jack Carter
Cc: llvm-commits
Subject: Re: [llvm] r181729 - Mips assembler: Assembler macro ADDIU $rs,imm

Hi Jack,

> This patch adds alias for addiu instruction which enables following syntax:
>
>     addiu $rs,imm
>
> The macro is translated as:
>
>     addiu $rs,$rs,imm

I'm not sure how generic this is in MIPS, but if there are more you
may want to look into the "TwoOperandAliasConstraint" field. It seems
to have been made to deal with this particular syntax variant.

Tim.