[llvm] r181729 - Mips assembler: Assembler macro ADDIU $rs,imm
Jack Carter
jack.carter at imgtec.com
Mon May 13 13:26:47 PDT 2013
Author: jacksprat
Date: Mon May 13 15:26:46 2013
New Revision: 181729
URL: http://llvm.org/viewvc/llvm-project?rev=181729&view=rev
Log:
Mips assembler: Assembler macro ADDIU $rs,imm
This patch adds alias for addiu instruction which enables following syntax:
addiu $rs,imm
The macro is translated as:
addiu $rs,$rs,imm
Contributer: Vladimir Medic
Modified:
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Mips/mips-alu-instructions.s
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=181729&r1=181728&r2=181729&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon May 13 15:26:46 2013
@@ -1095,7 +1095,8 @@ def : InstAlias<"mfc2 $rt, $rd",
(MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>;
def : InstAlias<"mtc2 $rt, $rd",
(MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>;
-
+def : InstAlias<"addiu $rs, $imm",
+ (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rs, simm16:$imm), 0>;
//===----------------------------------------------------------------------===//
// Assembler Pseudo Instructions
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/test/MC/Mips/mips-alu-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips-alu-instructions.s?rev=181729&r1=181728&r2=181729&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips-alu-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/mips-alu-instructions.s Mon May 13 15:26:46 2013
@@ -70,6 +70,7 @@
# CHECK: addiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x24]
# CHECK: addi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x20]
# CHECK: addiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x24]
+# CHECK: addiu $11, $11, 40 # encoding: [0x28,0x00,0x6b,0x25]
# CHECK: addu $9, $6, $7 # encoding: [0x21,0x48,0xc7,0x00]
# CHECK: madd $6, $7 # encoding: [0x00,0x00,0xc7,0x70]
# CHECK: maddu $6, $7 # encoding: [0x01,0x00,0xc7,0x70]
@@ -91,6 +92,7 @@
addu $9,$6,-15001
addi $9,$6,17767
addiu $9,$6,-15001
+ addiu $11,40
addu $9,$6,$7
madd $6,$7
maddu $6,$7
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