[llvm] r181597 - DAGCombiner: Generate a correct constant for vector types when folding (xor (and)) into (and (not)).

[Benjamin Kramer]

Author: d0k
Date: Fri May 10 09:09:52 2013
New Revision: 181597

URL: http://llvm.org/viewvc/llvm-project?rev=181597&view=rev
Log:
DAGCombiner: Generate a correct constant for vector types when folding (xor (and)) into (and (not)).

PR15948.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/X86/xor.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=181597&r1=181596&r2=181597&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri May 10 09:09:52 2013
@@ -3464,8 +3464,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N)
   if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
       N0->getOperand(1) == N1) {
     SDValue X = N0->getOperand(0);
-    SDValue NotX = DAG.getNode(ISD::XOR, X.getDebugLoc(), VT, X,
-      DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
+    SDValue NotX = DAG.getNOT(X.getDebugLoc(), X, VT);
     AddToWorkList(NotX.getNode());
     return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NotX, N1);
   }

Modified: llvm/trunk/test/CodeGen/X86/xor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/xor.ll?rev=181597&r1=181596&r2=181597&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/xor.ll (original)
+++ llvm/trunk/test/CodeGen/X86/xor.ll Fri May 10 09:09:52 2013
@@ -154,3 +154,14 @@ define i32 @test9(i32 %a) nounwind {
 ; X32:    notl	[[REG:%[a-z]+]]
 ; X32:    andl	{{.*}}[[REG:%[a-z]+]]
 }
+
+; PR15948
+define <4 x i32> @test10(<4 x i32> %a) nounwind {
+  %1 = and <4 x i32> %a, <i32 4096, i32 4096, i32 4096, i32 4096>
+  %2 = xor <4 x i32> %1, <i32 4096, i32 4096, i32 4096, i32 4096>
+  ret <4 x i32> %2
+; X64: test10:
+; X64:    andnps
+; X32: test10:
+; X32:    andnps
+}