[llvm] r180953 - Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.
Bill Wendling
wendling at apple.com
Thu May 2 14:45:16 PDT 2013
Jyotsna,
We're getting these failures on our buildbots after your check in. Could you investigate please?
******************** TEST 'LLVM :: CodeGen/Hexagon/absimm.ll' FAILED ********************
Script:
--
/Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.clang-x86_64-darwin-nobootstrap-RAincremental/clang-build/Release+Asserts/bin/llc -march=hexagon -mcpu=hexagonv4 < /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.clang-x86_64-darwin-nobootstrap-RAincremental/llvm/test/CodeGen/Hexagon/absimm.ll | /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.clang-x86_64-darwin11-nobootstrap-RAincremental/clang-build/Release+Asserts/bin/FileCheck /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.clang-x86_64-darwin-nobootstrap-RAincremental/llvm/test/CodeGen/Hexagon/absimm.ll
--
Exit Code: 2
Command Output (stderr):
--
0 llc 0x0000000103359f35 llvm::sys::PrintStackTrace(__sFILE*) + 37
1 llc 0x000000010335a5a9 _ZL13SignalHandleri + 713
2 libsystem_c.dylib 0x00007fff91b3dcfa _sigtramp + 26
3 llc 0x00000001030a86df llvm::TargetSchedModel::computeOperandLatency(llvm::MachineInstr const*, unsigned int, llvm::MachineInstr const*, unsigned int, bool) const + 303
4 llc 0x0000000102f475f5 llvm::VLIWPacketizerList::PacketizeMIs(llvm::MachineBasicBlock*, llvm::MachineBasicBlock::bundle_iterator<llvm::MachineInstr, llvm::ilist_iterator<llvm::MachineInstr> >, llvm::MachineBasicBlock::bundle_iterator<llvm::MachineInstr, llvm::ilist_iterator<llvm::MachineInstr> >) + 485
5 llc 0x00000001029a47c8 (anonymous namespace)::HexagonPacketizer::runOnMachineFunction(llvm::MachineFunction&) + 840
6 llc 0x0000000102fbe3ac llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 60
7 llc 0x00000001032f69b6 llvm::FPPassManager::runOnFunction(llvm::Function&) + 310
8 llc 0x00000001032f6c2b llvm::FPPassManager::runOnModule(llvm::Module&) + 59
9 llc 0x00000001032f6f18 llvm::MPPassManager::runOnModule(llvm::Module&) + 344
10 llc 0x00000001032f7556 llvm::PassManagerImpl::run(llvm::Module&) + 294
11 llc 0x00000001032f774d llvm::PassManager::run(llvm::Module&) + 13
12 llc 0x0000000102938b30 main + 5872
13 llc 0x0000000102937434 start + 52
Stack dump:
0. Program arguments: /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.clang-x86_64-darwin-nobootstrap-RAincremental/clang-build/Release+Asserts/bin/llc -march=hexagon -mcpu=hexagonv4
1. Running pass 'Function Pass Manager' on module '<stdin>'.
2. Running pass 'Hexagon Packetizer' on function '@f2'
FileCheck error: '-' is empty.
--
********************
-bw
On May 2, 2013, at 2:21 PM, Jyotsna Verma <jverma at codeaurora.org> wrote:
> Author: jverma
> Date: Thu May 2 16:21:57 2013
> New Revision: 180953
>
> URL: http://llvm.org/viewvc/llvm-project?rev=180953&view=rev
> Log:
> Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.
>
>
> Modified:
> llvm/trunk/lib/Target/Hexagon/Hexagon.td
> llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h
> llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
> llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp
>
> Modified: llvm/trunk/lib/Target/Hexagon/Hexagon.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Hexagon.td?rev=180953&r1=180952&r2=180953&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/Hexagon.td (original)
> +++ llvm/trunk/lib/Target/Hexagon/Hexagon.td Thu May 2 16:21:57 2013
> @@ -84,6 +84,30 @@ def getPredOpcode : InstrMapping {
> }
>
> //===----------------------------------------------------------------------===//
> +// Generate mapping table to relate predicate-true instructions with their
> +// predicate-false forms
> +//
> +def getFalsePredOpcode : InstrMapping {
> + let FilterClass = "PredRel";
> + let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken"];
> + let ColFields = ["PredSense"];
> + let KeyCol = ["true"];
> + let ValueCols = [["false"]];
> +}
> +
> +//===----------------------------------------------------------------------===//
> +// Generate mapping table to relate predicate-false instructions with their
> +// predicate-true forms
> +//
> +def getTruePredOpcode : InstrMapping {
> + let FilterClass = "PredRel";
> + let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken"];
> + let ColFields = ["PredSense"];
> + let KeyCol = ["false"];
> + let ValueCols = [["true"]];
> +}
> +
> +//===----------------------------------------------------------------------===//
> // Generate mapping table to relate predicated instructions with their .new
> // format.
> //
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=180953&r1=180952&r2=180953&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Thu May 2 16:21:57 2013
> @@ -625,110 +625,8 @@ bool HexagonInstrInfo::isExtended(const
> return false;
> }
>
> -bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
> - switch (MI->getOpcode()) {
> - default: return false;
> - // JMP_EQri
> - case Hexagon::JMP_EQriPt_nv_V4:
> - case Hexagon::JMP_EQriPnt_nv_V4:
> - case Hexagon::JMP_EQriNotPt_nv_V4:
> - case Hexagon::JMP_EQriNotPnt_nv_V4:
> - case Hexagon::JMP_EQriPt_ie_nv_V4:
> - case Hexagon::JMP_EQriPnt_ie_nv_V4:
> - case Hexagon::JMP_EQriNotPt_ie_nv_V4:
> - case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
> -
> - // JMP_EQri - with -1
> - case Hexagon::JMP_EQriPtneg_nv_V4:
> - case Hexagon::JMP_EQriPntneg_nv_V4:
> - case Hexagon::JMP_EQriNotPtneg_nv_V4:
> - case Hexagon::JMP_EQriNotPntneg_nv_V4:
> - case Hexagon::JMP_EQriPtneg_ie_nv_V4:
> - case Hexagon::JMP_EQriPntneg_ie_nv_V4:
> - case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
> - case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
> -
> - // JMP_EQrr
> - case Hexagon::JMP_EQrrPt_nv_V4:
> - case Hexagon::JMP_EQrrPnt_nv_V4:
> - case Hexagon::JMP_EQrrNotPt_nv_V4:
> - case Hexagon::JMP_EQrrNotPnt_nv_V4:
> - case Hexagon::JMP_EQrrPt_ie_nv_V4:
> - case Hexagon::JMP_EQrrPnt_ie_nv_V4:
> - case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
> - case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
> -
> - // JMP_GTri
> - case Hexagon::JMP_GTriPt_nv_V4:
> - case Hexagon::JMP_GTriPnt_nv_V4:
> - case Hexagon::JMP_GTriNotPt_nv_V4:
> - case Hexagon::JMP_GTriNotPnt_nv_V4:
> - case Hexagon::JMP_GTriPt_ie_nv_V4:
> - case Hexagon::JMP_GTriPnt_ie_nv_V4:
> - case Hexagon::JMP_GTriNotPt_ie_nv_V4:
> - case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
> -
> - // JMP_GTri - with -1
> - case Hexagon::JMP_GTriPtneg_nv_V4:
> - case Hexagon::JMP_GTriPntneg_nv_V4:
> - case Hexagon::JMP_GTriNotPtneg_nv_V4:
> - case Hexagon::JMP_GTriNotPntneg_nv_V4:
> - case Hexagon::JMP_GTriPtneg_ie_nv_V4:
> - case Hexagon::JMP_GTriPntneg_ie_nv_V4:
> - case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
> - case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
> -
> - // JMP_GTrr
> - case Hexagon::JMP_GTrrPt_nv_V4:
> - case Hexagon::JMP_GTrrPnt_nv_V4:
> - case Hexagon::JMP_GTrrNotPt_nv_V4:
> - case Hexagon::JMP_GTrrNotPnt_nv_V4:
> - case Hexagon::JMP_GTrrPt_ie_nv_V4:
> - case Hexagon::JMP_GTrrPnt_ie_nv_V4:
> - case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
> - case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
> -
> - // JMP_GTrrdn
> - case Hexagon::JMP_GTrrdnPt_nv_V4:
> - case Hexagon::JMP_GTrrdnPnt_nv_V4:
> - case Hexagon::JMP_GTrrdnNotPt_nv_V4:
> - case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
> - case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
> - case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
> - case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
> - case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
> -
> - // JMP_GTUri
> - case Hexagon::JMP_GTUriPt_nv_V4:
> - case Hexagon::JMP_GTUriPnt_nv_V4:
> - case Hexagon::JMP_GTUriNotPt_nv_V4:
> - case Hexagon::JMP_GTUriNotPnt_nv_V4:
> - case Hexagon::JMP_GTUriPt_ie_nv_V4:
> - case Hexagon::JMP_GTUriPnt_ie_nv_V4:
> - case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
> - case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
> -
> - // JMP_GTUrr
> - case Hexagon::JMP_GTUrrPt_nv_V4:
> - case Hexagon::JMP_GTUrrPnt_nv_V4:
> - case Hexagon::JMP_GTUrrNotPt_nv_V4:
> - case Hexagon::JMP_GTUrrNotPnt_nv_V4:
> - case Hexagon::JMP_GTUrrPt_ie_nv_V4:
> - case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
> - case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
> - case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
> -
> - // JMP_GTUrrdn
> - case Hexagon::JMP_GTUrrdnPt_nv_V4:
> - case Hexagon::JMP_GTUrrdnPnt_nv_V4:
> - case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
> - case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
> - case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
> - case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
> - case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
> - case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
> - return true;
> - }
> +bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const {
> + return MI->getDesc().isBranch();
> }
>
> bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
> @@ -1032,6 +930,12 @@ bool HexagonInstrInfo::isPredicable(Mach
> // cNotPt ---> cNotPt_nv
> // cPt ---> cPt_nv
> unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
> + int InvPredOpcode;
> + InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
> + : Hexagon::getTruePredOpcode(Opc);
> + if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
> + return InvPredOpcode;
> +
> switch(Opc) {
> default: llvm_unreachable("Unexpected predicated instruction");
> case Hexagon::TFR_cPt:
> @@ -1364,117 +1268,6 @@ unsigned HexagonInstrInfo::getInvertedPr
> return Hexagon::DEALLOC_RET_cNotPt_V4;
> case Hexagon::DEALLOC_RET_cNotPt_V4:
> return Hexagon::DEALLOC_RET_cPt_V4;
> -
> - // New Value Jump.
> - // JMPEQ_ri - with -1.
> - case Hexagon::JMP_EQriPtneg_nv_V4:
> - return Hexagon::JMP_EQriNotPtneg_nv_V4;
> - case Hexagon::JMP_EQriNotPtneg_nv_V4:
> - return Hexagon::JMP_EQriPtneg_nv_V4;
> -
> - case Hexagon::JMP_EQriPntneg_nv_V4:
> - return Hexagon::JMP_EQriNotPntneg_nv_V4;
> - case Hexagon::JMP_EQriNotPntneg_nv_V4:
> - return Hexagon::JMP_EQriPntneg_nv_V4;
> -
> - // JMPEQ_ri.
> - case Hexagon::JMP_EQriPt_nv_V4:
> - return Hexagon::JMP_EQriNotPt_nv_V4;
> - case Hexagon::JMP_EQriNotPt_nv_V4:
> - return Hexagon::JMP_EQriPt_nv_V4;
> -
> - case Hexagon::JMP_EQriPnt_nv_V4:
> - return Hexagon::JMP_EQriNotPnt_nv_V4;
> - case Hexagon::JMP_EQriNotPnt_nv_V4:
> - return Hexagon::JMP_EQriPnt_nv_V4;
> -
> - // JMPEQ_rr.
> - case Hexagon::JMP_EQrrPt_nv_V4:
> - return Hexagon::JMP_EQrrNotPt_nv_V4;
> - case Hexagon::JMP_EQrrNotPt_nv_V4:
> - return Hexagon::JMP_EQrrPt_nv_V4;
> -
> - case Hexagon::JMP_EQrrPnt_nv_V4:
> - return Hexagon::JMP_EQrrNotPnt_nv_V4;
> - case Hexagon::JMP_EQrrNotPnt_nv_V4:
> - return Hexagon::JMP_EQrrPnt_nv_V4;
> -
> - // JMPGT_ri - with -1.
> - case Hexagon::JMP_GTriPtneg_nv_V4:
> - return Hexagon::JMP_GTriNotPtneg_nv_V4;
> - case Hexagon::JMP_GTriNotPtneg_nv_V4:
> - return Hexagon::JMP_GTriPtneg_nv_V4;
> -
> - case Hexagon::JMP_GTriPntneg_nv_V4:
> - return Hexagon::JMP_GTriNotPntneg_nv_V4;
> - case Hexagon::JMP_GTriNotPntneg_nv_V4:
> - return Hexagon::JMP_GTriPntneg_nv_V4;
> -
> - // JMPGT_ri.
> - case Hexagon::JMP_GTriPt_nv_V4:
> - return Hexagon::JMP_GTriNotPt_nv_V4;
> - case Hexagon::JMP_GTriNotPt_nv_V4:
> - return Hexagon::JMP_GTriPt_nv_V4;
> -
> - case Hexagon::JMP_GTriPnt_nv_V4:
> - return Hexagon::JMP_GTriNotPnt_nv_V4;
> - case Hexagon::JMP_GTriNotPnt_nv_V4:
> - return Hexagon::JMP_GTriPnt_nv_V4;
> -
> - // JMPGT_rr.
> - case Hexagon::JMP_GTrrPt_nv_V4:
> - return Hexagon::JMP_GTrrNotPt_nv_V4;
> - case Hexagon::JMP_GTrrNotPt_nv_V4:
> - return Hexagon::JMP_GTrrPt_nv_V4;
> -
> - case Hexagon::JMP_GTrrPnt_nv_V4:
> - return Hexagon::JMP_GTrrNotPnt_nv_V4;
> - case Hexagon::JMP_GTrrNotPnt_nv_V4:
> - return Hexagon::JMP_GTrrPnt_nv_V4;
> -
> - // JMPGT_rrdn.
> - case Hexagon::JMP_GTrrdnPt_nv_V4:
> - return Hexagon::JMP_GTrrdnNotPt_nv_V4;
> - case Hexagon::JMP_GTrrdnNotPt_nv_V4:
> - return Hexagon::JMP_GTrrdnPt_nv_V4;
> -
> - case Hexagon::JMP_GTrrdnPnt_nv_V4:
> - return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
> - case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
> - return Hexagon::JMP_GTrrdnPnt_nv_V4;
> -
> - // JMPGTU_ri.
> - case Hexagon::JMP_GTUriPt_nv_V4:
> - return Hexagon::JMP_GTUriNotPt_nv_V4;
> - case Hexagon::JMP_GTUriNotPt_nv_V4:
> - return Hexagon::JMP_GTUriPt_nv_V4;
> -
> - case Hexagon::JMP_GTUriPnt_nv_V4:
> - return Hexagon::JMP_GTUriNotPnt_nv_V4;
> - case Hexagon::JMP_GTUriNotPnt_nv_V4:
> - return Hexagon::JMP_GTUriPnt_nv_V4;
> -
> - // JMPGTU_rr.
> - case Hexagon::JMP_GTUrrPt_nv_V4:
> - return Hexagon::JMP_GTUrrNotPt_nv_V4;
> - case Hexagon::JMP_GTUrrNotPt_nv_V4:
> - return Hexagon::JMP_GTUrrPt_nv_V4;
> -
> - case Hexagon::JMP_GTUrrPnt_nv_V4:
> - return Hexagon::JMP_GTUrrNotPnt_nv_V4;
> - case Hexagon::JMP_GTUrrNotPnt_nv_V4:
> - return Hexagon::JMP_GTUrrPnt_nv_V4;
> -
> - // JMPGTU_rrdn.
> - case Hexagon::JMP_GTUrrdnPt_nv_V4:
> - return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
> - case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
> - return Hexagon::JMP_GTUrrdnPt_nv_V4;
> -
> - case Hexagon::JMP_GTUrrdnPnt_nv_V4:
> - return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
> - case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
> - return Hexagon::JMP_GTUrrdnPnt_nv_V4;
> }
> }
>
> @@ -1503,12 +1296,7 @@ getMatchingCondBranchOpcode(int Opc, boo
> case Hexagon::JMP:
> return !invertPredicate ? Hexagon::JMP_t :
> Hexagon::JMP_f;
> - case Hexagon::JMP_EQrrPt_nv_V4:
> - return !invertPredicate ? Hexagon::JMP_EQrrPt_nv_V4 :
> - Hexagon::JMP_EQrrNotPt_nv_V4;
> - case Hexagon::JMP_EQriPt_nv_V4:
> - return !invertPredicate ? Hexagon::JMP_EQriPt_nv_V4 :
> - Hexagon::JMP_EQriNotPt_nv_V4;
> +
> case Hexagon::COMBINE_rr:
> return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
> Hexagon::COMBINE_rr_cNotPt;
> @@ -1889,13 +1677,41 @@ isProfitableToIfCvt(MachineBasicBlock &T
> return true;
> }
>
> -
> +// Returns true if an instruction is predicated irrespective of the predicate
> +// sense. For example, all of the following will return true.
> +// if (p0) R1 = add(R2, R3)
> +// if (!p0) R1 = add(R2, R3)
> +// if (p0.new) R1 = add(R2, R3)
> +// if (!p0.new) R1 = add(R2, R3)
> bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
> const uint64_t F = MI->getDesc().TSFlags;
>
> return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
> }
>
> +bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
> + const uint64_t F = get(Opcode).TSFlags;
> +
> + return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
> +}
> +
> +bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
> + const uint64_t F = MI->getDesc().TSFlags;
> +
> + assert(isPredicated(MI));
> + return (!((F >> HexagonII::PredicatedFalsePos) &
> + HexagonII::PredicatedFalseMask));
> +}
> +
> +bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
> + const uint64_t F = get(Opcode).TSFlags;
> +
> + // Make sure that the instruction is predicated.
> + assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
> + return (!((F >> HexagonII::PredicatedFalsePos) &
> + HexagonII::PredicatedFalseMask));
> +}
> +
> bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
> const uint64_t F = MI->getDesc().TSFlags;
>
> @@ -1903,6 +1719,13 @@ bool HexagonInstrInfo::isPredicatedNew(c
> return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
> }
>
> +bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
> + const uint64_t F = get(Opcode).TSFlags;
> +
> + assert(isPredicated(Opcode));
> + return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
> +}
> +
> bool
> HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
> std::vector<MachineOperand> &Pred) const {
> @@ -2371,6 +2194,18 @@ isConditionalStore (const MachineInstr*
> }
> }
>
> +
> +bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
> + if (isNewValue(MI) && isBranch(MI))
> + return true;
> + return false;
> +}
> +
> +bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
> + const uint64_t F = MI->getDesc().TSFlags;
> + return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
> +}
> +
> // Returns true, if any one of the operands is a dot new
> // insn, whether it is predicated dot new or register dot new.
> bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h?rev=180953&r1=180952&r2=180953&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h Thu May 2 16:21:57 2013
> @@ -113,6 +113,7 @@ public:
>
> unsigned createVR(MachineFunction* MF, MVT VT) const;
>
> + virtual bool isBranch(const MachineInstr *MI) const;
> virtual bool isPredicable(MachineInstr *MI) const;
> virtual bool
> PredicateInstruction(MachineInstr *MI,
> @@ -129,7 +130,11 @@ public:
> const BranchProbability &Probability) const;
>
> virtual bool isPredicated(const MachineInstr *MI) const;
> + virtual bool isPredicated(unsigned Opcode) const;
> + virtual bool isPredicatedTrue(const MachineInstr *MI) const;
> + virtual bool isPredicatedTrue(unsigned Opcode) const;
> virtual bool isPredicatedNew(const MachineInstr *MI) const;
> + virtual bool isPredicatedNew(unsigned Opcode) const;
> virtual bool DefinesPredicate(MachineInstr *MI,
> std::vector<MachineOperand> &Pred) const;
> virtual bool
> @@ -178,6 +183,7 @@ public:
> bool isConditionalLoad (const MachineInstr* MI) const;
> bool isConditionalStore(const MachineInstr* MI) const;
> bool isNewValueInst(const MachineInstr* MI) const;
> + bool isNewValue(const MachineInstr* MI) const;
> bool isDotNewInst(const MachineInstr* MI) const;
> bool isDeallocRet(const MachineInstr *MI) const;
> unsigned getInvertedPredicatedOpcode(const int Opc) const;
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=180953&r1=180952&r2=180953&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td Thu May 2 16:21:57 2013
> @@ -967,181 +967,195 @@ defm POST_STwri: ST_PostInc_nv <"memw",
> // NV/J +
> //===----------------------------------------------------------------------===//
>
> -multiclass NVJ_type_basic_reg<string NotStr, string OpcStr, string TakenStr> {
> - def _ie_nv_V4 : NVInst_V4<(outs),
> - (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
> - !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
> - !strconcat("($src1.new, $src2)) jump:",
> - !strconcat(TakenStr, " $offset"))))),
> - []>,
> - Requires<[HasV4T]>;
> -
> - def _nv_V4 : NVInst_V4<(outs),
> - (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
> - !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
> - !strconcat("($src1.new, $src2)) jump:",
> - !strconcat(TakenStr, " $offset"))))),
> - []>,
> - Requires<[HasV4T]>;
> -}
> -
> -multiclass NVJ_type_basic_2ndDotNew<string NotStr, string OpcStr,
> - string TakenStr> {
> - def _ie_nv_V4 : NVInst_V4<(outs),
> - (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
> - !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
> - !strconcat("($src1, $src2.new)) jump:",
> - !strconcat(TakenStr, " $offset"))))),
> - []>,
> - Requires<[HasV4T]>;
> -
> - def _nv_V4 : NVInst_V4<(outs),
> - (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
> - !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
> - !strconcat("($src1, $src2.new)) jump:",
> - !strconcat(TakenStr, " $offset"))))),
> - []>,
> - Requires<[HasV4T]>;
> -}
> -
> -multiclass NVJ_type_basic_imm<string NotStr, string OpcStr, string TakenStr> {
> - def _ie_nv_V4 : NVInst_V4<(outs),
> - (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
> - !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
> - !strconcat("($src1.new, #$src2)) jump:",
> - !strconcat(TakenStr, " $offset"))))),
> - []>,
> - Requires<[HasV4T]>;
> -
> - def _nv_V4 : NVInst_V4<(outs),
> - (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
> - !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
> - !strconcat("($src1.new, #$src2)) jump:",
> - !strconcat(TakenStr, " $offset"))))),
> - []>,
> - Requires<[HasV4T]>;
> -}
> -
> -multiclass NVJ_type_basic_neg<string NotStr, string OpcStr, string TakenStr> {
> - def _ie_nv_V4 : NVInst_V4<(outs),
> - (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
> - !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
> - !strconcat("($src1.new, #$src2)) jump:",
> - !strconcat(TakenStr, " $offset"))))),
> - []>,
> - Requires<[HasV4T]>;
> -
> - def _nv_V4 : NVInst_V4<(outs),
> - (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
> - !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
> - !strconcat("($src1.new, #$src2)) jump:",
> - !strconcat(TakenStr, " $offset"))))),
> - []>,
> - Requires<[HasV4T]>;
> -}
> -
> -multiclass NVJ_type_basic_tstbit<string NotStr, string OpcStr,
> - string TakenStr> {
> - def _ie_nv_V4 : NVInst_V4<(outs),
> - (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
> - !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
> - !strconcat("($src1.new, #$src2)) jump:",
> - !strconcat(TakenStr, " $offset"))))),
> - []>,
> - Requires<[HasV4T]>;
> -
> - def _nv_V4 : NVInst_V4<(outs),
> - (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
> - !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
> - !strconcat("($src1.new, #$src2)) jump:",
> - !strconcat(TakenStr, " $offset"))))),
> - []>,
> - Requires<[HasV4T]>;
> -}
> -
> -// Multiclass for regular dot new of Ist operand register.
> -multiclass NVJ_type_br_pred_reg<string NotStr, string OpcStr> {
> - defm Pt : NVJ_type_basic_reg<NotStr, OpcStr, "t">;
> - defm Pnt : NVJ_type_basic_reg<NotStr, OpcStr, "nt">;
> -}
> -
> -// Multiclass for dot new of 2nd operand register.
> -multiclass NVJ_type_br_pred_2ndDotNew<string NotStr, string OpcStr> {
> - defm Pt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "t">;
> - defm Pnt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "nt">;
> -}
> +//===----------------------------------------------------------------------===//
> +// multiclass/template class for the new-value compare jumps with the register
> +// operands.
> +//===----------------------------------------------------------------------===//
>
> -// Multiclass for 2nd operand immediate, including -1.
> -multiclass NVJ_type_br_pred_imm<string NotStr, string OpcStr> {
> - defm Pt : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
> - defm Pnt : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
> - defm Ptneg : NVJ_type_basic_neg<NotStr, OpcStr, "t">;
> - defm Pntneg : NVJ_type_basic_neg<NotStr, OpcStr, "nt">;
> +let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in
> +class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
> + bit isNegCond, bit isTaken>
> + : NVInst_V4<(outs),
> + (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
> + "if ("#!if(isNegCond, "!","")#mnemonic#
> + "($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")#
> + "$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:"
> + #!if(isTaken, "t","nt")#" $offset",
> + []>, Requires<[HasV4T]> {
> +
> + bits<5> src1;
> + bits<5> src2;
> + bits<3> Ns; // New-Value Operand
> + bits<5> RegOp; // Non New-Value Operand
> + bits<11> offset;
> +
> + let isBrTaken = !if(isTaken, "true", "false");
> + let isPredicatedFalse = isNegCond;
> +
> + let Ns = !if(!eq(NvOpNum, 0), src1{2-0}, src2{2-0});
> + let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
> +
> + let IClass = 0b0010;
> + let Inst{26} = 0b0;
> + let Inst{25-23} = majOp;
> + let Inst{22} = isNegCond;
> + let Inst{18-16} = Ns;
> + let Inst{13} = isTaken;
> + let Inst{12-8} = RegOp;
> + let Inst{21-20} = offset{10-9};
> + let Inst{7-1} = offset{8-2};
> }
>
> -// Multiclass for 2nd operand immediate, excluding -1.
> -multiclass NVJ_type_br_pred_imm_only<string NotStr, string OpcStr> {
> - defm Pt : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
> - defm Pnt : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
> -}
>
> -// Multiclass for tstbit, where 2nd operand is always #0.
> -multiclass NVJ_type_br_pred_tstbit<string NotStr, string OpcStr> {
> - defm Pt : NVJ_type_basic_tstbit<NotStr, OpcStr, "t">;
> - defm Pnt : NVJ_type_basic_tstbit<NotStr, OpcStr, "nt">;
> +multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum,
> + bit isNegCond> {
> + // Branch not taken:
> + def _nt_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>;
> + // Branch taken:
> + def _t_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>;
> +}
> +
> +// NvOpNum = 0 -> First Operand is a new-value Register
> +// NvOpNum = 1 -> Second Operand is a new-value Register
> +
> +multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
> + bit NvOpNum> {
> + let BaseOpcode = BaseOp#_NVJ in {
> + defm _t_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond
> + defm _f_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond
> + }
> }
>
> -// Multiclass for GT.
> -multiclass NVJ_type_rr_ri<string OpcStr> {
> - defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
> - defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
> - defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
> - defm rrdn : NVJ_type_br_pred_2ndDotNew<"", OpcStr>;
> - defm riNot : NVJ_type_br_pred_imm<"!", OpcStr>;
> - defm ri : NVJ_type_br_pred_imm<"", OpcStr>;
> +// if ([!]cmp.eq(Ns.new,Rt)) jump:[n]t #r9:2
> +// if ([!]cmp.gt(Ns.new,Rt)) jump:[n]t #r9:2
> +// if ([!]cmp.gtu(Ns.new,Rt)) jump:[n]t #r9:2
> +// if ([!]cmp.gt(Rt,Ns.new)) jump:[n]t #r9:2
> +// if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2
> +
> +let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
> + Defs = [PC], neverHasSideEffects = 1, validSubTargets = HasV4SubT in {
> + defm CMPEQrr : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
> + defm CMPGTrr : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
> + defm CMPGTUrr : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
> + defm CMPLTrr : NVJrr_base<"cmp.gt", "CMPLT", 0b011, 1>, PredRel;
> + defm CMPLTUrr : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel;
> }
>
> -// Multiclass for EQ.
> -multiclass NVJ_type_rr_ri_no_2ndDotNew<string OpcStr> {
> - defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
> - defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
> - defm riNot : NVJ_type_br_pred_imm<"!", OpcStr>;
> - defm ri : NVJ_type_br_pred_imm<"", OpcStr>;
> +//===----------------------------------------------------------------------===//
> +// multiclass/template class for the new-value compare jumps instruction
> +// with a register and an unsigned immediate (U5) operand.
> +//===----------------------------------------------------------------------===//
> +
> +let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in
> +class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
> + bit isTaken>
> + : NVInst_V4<(outs),
> + (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
> + "if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
> + #!if(isTaken, "t","nt")#" $offset",
> + []>, Requires<[HasV4T]> {
> +
> + let isPredicatedFalse = isNegCond;
> + let isBrTaken = !if(isTaken, "true", "false");
> +
> + bits<3> src1;
> + bits<5> src2;
> + bits<11> offset;
> +
> + let IClass = 0b0010;
> + let Inst{26} = 0b1;
> + let Inst{25-23} = majOp;
> + let Inst{22} = isNegCond;
> + let Inst{18-16} = src1;
> + let Inst{13} = isTaken;
> + let Inst{12-8} = src2;
> + let Inst{21-20} = offset{10-9};
> + let Inst{7-1} = offset{8-2};
> +}
> +
> +multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> {
> + // Branch not taken:
> + def _nt_V4: NVJri_template<mnemonic, majOp, isNegCond, 0>;
> + // Branch taken:
> + def _t_V4: NVJri_template<mnemonic, majOp, isNegCond, 1>;
> +}
> +
> +multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
> + let BaseOpcode = BaseOp#_NVJri in {
> + defm _t_Jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond
> + defm _f_Jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond
> + }
> }
>
> -// Multiclass for GTU.
> -multiclass NVJ_type_rr_ri_no_nOne<string OpcStr> {
> - defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
> - defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
> - defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
> - defm rrdn : NVJ_type_br_pred_2ndDotNew<"", OpcStr>;
> - defm riNot : NVJ_type_br_pred_imm_only<"!", OpcStr>;
> - defm ri : NVJ_type_br_pred_imm_only<"", OpcStr>;
> +// if ([!]cmp.eq(Ns.new,#U5)) jump:[n]t #r9:2
> +// if ([!]cmp.gt(Ns.new,#U5)) jump:[n]t #r9:2
> +// if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2
> +
> +let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
> + Defs = [PC], neverHasSideEffects = 1, validSubTargets = HasV4SubT in {
> + defm CMPEQri : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
> + defm CMPGTri : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
> + defm CMPGTUri : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
> }
>
> -// Multiclass for tstbit.
> -multiclass NVJ_type_r0<string OpcStr> {
> - defm r0Not : NVJ_type_br_pred_tstbit<"!", OpcStr>;
> - defm r0 : NVJ_type_br_pred_tstbit<"", OpcStr>;
> - }
> -
> -// Base Multiclass for New Value Jump.
> -multiclass NVJ_type {
> - defm GT : NVJ_type_rr_ri<"cmp.gt">;
> - defm EQ : NVJ_type_rr_ri_no_2ndDotNew<"cmp.eq">;
> - defm GTU : NVJ_type_rr_ri_no_nOne<"cmp.gtu">;
> - defm TSTBIT : NVJ_type_r0<"tstbit">;
> +//===----------------------------------------------------------------------===//
> +// multiclass/template class for the new-value compare jumps instruction
> +// with a register and an hardcoded 0/-1 immediate value.
> +//===----------------------------------------------------------------------===//
> +
> +let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11 in
> +class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
> + bit isNegCond, bit isTaken>
> + : NVInst_V4<(outs),
> + (ins IntRegs:$src1, brtarget:$offset),
> + "if ("#!if(isNegCond, "!","")#mnemonic
> + #"($src1.new, #"#ImmVal#")) jump:"
> + #!if(isTaken, "t","nt")#" $offset",
> + []>, Requires<[HasV4T]> {
> +
> + let isPredicatedFalse = isNegCond;
> + let isBrTaken = !if(isTaken, "true", "false");
> +
> + bits<3> src1;
> + bits<11> offset;
> + let IClass = 0b0010;
> + let Inst{26} = 0b1;
> + let Inst{25-23} = majOp;
> + let Inst{22} = isNegCond;
> + let Inst{18-16} = src1;
> + let Inst{13} = isTaken;
> + let Inst{21-20} = offset{10-9};
> + let Inst{7-1} = offset{8-2};
> +}
> +
> +multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal,
> + bit isNegCond> {
> + // Branch not taken:
> + def _nt_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>;
> + // Branch taken:
> + def _t_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>;
> +}
> +
> +multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
> + string ImmVal> {
> + let BaseOpcode = BaseOp#_NVJ_ConstImm in {
> + defm _t_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True cond
> + defm _f_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False Cond
> + }
> }
>
> -let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
> - defm JMP_ : NVJ_type;
> +// if ([!]tstbit(Ns.new,#0)) jump:[n]t #r9:2
> +// if ([!]cmp.eq(Ns.new,#-1)) jump:[n]t #r9:2
> +// if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2
> +
> +let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
> + Defs = [PC], neverHasSideEffects = 1 in {
> + defm TSTBIT0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
> + defm CMPEQn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
> + defm CMPGTn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
> }
>
> //===----------------------------------------------------------------------===//
> -// NV/J -
> -//===----------------------------------------------------------------------===//
> -
> -//===----------------------------------------------------------------------===//
> // XTYPE/ALU +
> //===----------------------------------------------------------------------===//
>
> @@ -3007,9 +3021,10 @@ def : Pat <(i32 (load (HexagonCONST32_GP
>
>
> // Transfer global address into a register
> -let AddedComplexity=50, isMoveImm = 1, isReMaterializable = 1 in
> -def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$src1),
> - "$dst = ##$src1",
> +let isExtended = 1, opExtendable = 1, AddedComplexity=50, isMoveImm = 1,
> +isAsCheapAsAMove = 1, isReMaterializable = 1, validSubTargets = HasV4SubT in
> +def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
> + "$dst = #$src1",
> [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
> Requires<[HasV4T]>;
>
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp?rev=180953&r1=180952&r2=180953&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp Thu May 2 16:21:57 2013
> @@ -22,29 +22,31 @@
> //
> //===----------------------------------------------------------------------===//
> #define DEBUG_TYPE "hexagon-nvj"
> -#include "Hexagon.h"
> -#include "HexagonInstrInfo.h"
> -#include "HexagonMachineFunctionInfo.h"
> -#include "HexagonRegisterInfo.h"
> -#include "HexagonSubtarget.h"
> -#include "HexagonTargetMachine.h"
> +#include "llvm/PassSupport.h"
> +#include "llvm/Support/Compiler.h"
> +#include "llvm/Support/Debug.h"
> #include "llvm/ADT/DenseMap.h"
> #include "llvm/ADT/Statistic.h"
> -#include "llvm/CodeGen/LiveVariables.h"
> -#include "llvm/CodeGen/MachineFunctionAnalysis.h"
> -#include "llvm/CodeGen/MachineFunctionPass.h"
> -#include "llvm/CodeGen/MachineInstrBuilder.h"
> -#include "llvm/CodeGen/MachineRegisterInfo.h"
> #include "llvm/CodeGen/Passes.h"
> #include "llvm/CodeGen/ScheduleDAGInstrs.h"
> -#include "llvm/PassSupport.h"
> -#include "llvm/Support/CommandLine.h"
> -#include "llvm/Support/Compiler.h"
> -#include "llvm/Support/Debug.h"
> -#include "llvm/Target/TargetInstrInfo.h"
> +#include "llvm/CodeGen/MachineInstrBuilder.h"
> +#include "llvm/CodeGen/MachineFunctionPass.h"
> +#include "llvm/CodeGen/LiveVariables.h"
> +#include "llvm/CodeGen/MachineRegisterInfo.h"
> +#include "llvm/CodeGen/MachineFunctionAnalysis.h"
> #include "llvm/Target/TargetMachine.h"
> +#include "llvm/Target/TargetInstrInfo.h"
> #include "llvm/Target/TargetRegisterInfo.h"
> +#include "Hexagon.h"
> +#include "HexagonTargetMachine.h"
> +#include "HexagonRegisterInfo.h"
> +#include "HexagonSubtarget.h"
> +#include "HexagonInstrInfo.h"
> +#include "HexagonMachineFunctionInfo.h"
> +
> #include <map>
> +
> +#include "llvm/Support/CommandLine.h"
> using namespace llvm;
>
> STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
> @@ -57,6 +59,11 @@ static cl::opt<bool> DisableNewValueJump
> cl::ZeroOrMore, cl::init(false),
> cl::desc("Disable New Value Jumps"));
>
> +namespace llvm {
> + void initializeHexagonNewValueJumpPass(PassRegistry&);
> +}
> +
> +
> namespace {
> struct HexagonNewValueJump : public MachineFunctionPass {
> const HexagonInstrInfo *QII;
> @@ -65,7 +72,9 @@ namespace {
> public:
> static char ID;
>
> - HexagonNewValueJump() : MachineFunctionPass(ID) { }
> + HexagonNewValueJump() : MachineFunctionPass(ID) {
> + initializeHexagonNewValueJumpPass(*PassRegistry::getPassRegistry());
> + }
>
> virtual void getAnalysisUsage(AnalysisUsage &AU) const {
> AU.addRequired<MachineBranchProbabilityInfo>();
> @@ -88,6 +97,13 @@ namespace {
>
> char HexagonNewValueJump::ID = 0;
>
> +INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj",
> + "Hexagon NewValueJump", false, false)
> +INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
> +INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj",
> + "Hexagon NewValueJump", false, false)
> +
> +
> // We have identified this II could be feeder to NVJ,
> // verify that it can be.
> static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
> @@ -219,7 +235,7 @@ static bool canCompareBeNewValueJump(con
> return false;
> }
>
> - unsigned cmpReg1, cmpOp2;
> + unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning.
> cmpReg1 = MI->getOperand(1).getReg();
>
> if (secondReg) {
> @@ -285,43 +301,48 @@ static unsigned getNewValueJumpOpcode(Ma
>
> switch (MI->getOpcode()) {
> case Hexagon::CMPEQrr:
> - return taken ? Hexagon::JMP_EQrrPt_nv_V4 : Hexagon::JMP_EQrrPnt_nv_V4;
> + return taken ? Hexagon::CMPEQrr_t_Jumpnv_t_V4
> + : Hexagon::CMPEQrr_t_Jumpnv_nt_V4;
>
> case Hexagon::CMPEQri: {
> if (reg >= 0)
> - return taken ? Hexagon::JMP_EQriPt_nv_V4 : Hexagon::JMP_EQriPnt_nv_V4;
> + return taken ? Hexagon::CMPEQri_t_Jumpnv_t_V4
> + : Hexagon::CMPEQri_t_Jumpnv_nt_V4;
> else
> - return taken ? Hexagon::JMP_EQriPtneg_nv_V4
> - : Hexagon::JMP_EQriPntneg_nv_V4;
> + return taken ? Hexagon::CMPEQn1_t_Jumpnv_t_V4
> + : Hexagon::CMPEQn1_t_Jumpnv_nt_V4;
> }
>
> case Hexagon::CMPGTrr: {
> if (secondRegNewified)
> - return taken ? Hexagon::JMP_GTrrdnPt_nv_V4
> - : Hexagon::JMP_GTrrdnPnt_nv_V4;
> + return taken ? Hexagon::CMPLTrr_t_Jumpnv_t_V4
> + : Hexagon::CMPLTrr_t_Jumpnv_nt_V4;
> else
> - return taken ? Hexagon::JMP_GTrrPt_nv_V4
> - : Hexagon::JMP_GTrrPnt_nv_V4;
> + return taken ? Hexagon::CMPGTrr_t_Jumpnv_t_V4
> + : Hexagon::CMPGTrr_t_Jumpnv_nt_V4;
> }
>
> case Hexagon::CMPGTri: {
> if (reg >= 0)
> - return taken ? Hexagon::JMP_GTriPt_nv_V4 : Hexagon::JMP_GTriPnt_nv_V4;
> + return taken ? Hexagon::CMPGTri_t_Jumpnv_t_V4
> + : Hexagon::CMPGTri_t_Jumpnv_nt_V4;
> else
> - return taken ? Hexagon::JMP_GTriPtneg_nv_V4
> - : Hexagon::JMP_GTriPntneg_nv_V4;
> + return taken ? Hexagon::CMPGTn1_t_Jumpnv_t_V4
> + : Hexagon::CMPGTn1_t_Jumpnv_nt_V4;
> }
>
> case Hexagon::CMPGTUrr: {
> if (secondRegNewified)
> - return taken ? Hexagon::JMP_GTUrrdnPt_nv_V4
> - : Hexagon::JMP_GTUrrdnPnt_nv_V4;
> + return taken ? Hexagon::CMPLTUrr_t_Jumpnv_t_V4
> + : Hexagon::CMPLTUrr_t_Jumpnv_nt_V4;
> else
> - return taken ? Hexagon::JMP_GTUrrPt_nv_V4 : Hexagon::JMP_GTUrrPnt_nv_V4;
> + return taken ? Hexagon::CMPGTUrr_t_Jumpnv_t_V4
> + : Hexagon::CMPGTUrr_t_Jumpnv_nt_V4;
> }
>
> case Hexagon::CMPGTUri:
> - return taken ? Hexagon::JMP_GTUriPt_nv_V4 : Hexagon::JMP_GTUriPnt_nv_V4;
> + return taken ? Hexagon::CMPGTUri_t_Jumpnv_t_V4
> + : Hexagon::CMPGTUri_t_Jumpnv_nt_V4;
>
> default:
> llvm_unreachable("Could not find matching New Value Jump instruction.");
>
>
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