[llvm] r180751 - R600: config section now reports use of killgt
Tom Stellard
tom at stellard.net
Thu May 2 10:20:06 PDT 2013
On Thu, May 02, 2013 at 09:49:40AM -0700, Vincent Lejeune wrote:
> Hi,
>
> Here is a patch that add a test for this commit.
> The 2 other patches change the asm output of r600 target,
> and as a side effect they make already existing tests check that Alu are correctly packetized and that literals immediatly follow instructions that use them.
> I'm working on tests for TEX/VTX too, they'll come later.
>
Patches 2 and 3 are:
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
I have a few questions about patch 1.
> From c422518bf586d2f88efa139814d27333f1dc922e Mon Sep 17 00:00:00 2001
> From: Vincent Lejeune <vljn at ovi.com>
> Date: Wed, 1 May 2013 18:26:34 +0200
> Subject: [PATCH 1/3] R600: Prettier asmPrint of Alu
>
> ---
> lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp | 33 ++++++++++++++++++--
> lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h | 4 ++-
> lib/Target/R600/R600Instructions.td | 15 ++++-----
> lib/Target/R600/R600RegisterInfo.td | 6 ++--
> test/CodeGen/R600/add.ll | 6 ++--
> test/CodeGen/R600/and.ll | 6 ++--
> .../R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll | 4 +--
> test/CodeGen/R600/fabs.ll | 2 +-
> test/CodeGen/R600/fadd.ll | 8 ++---
> test/CodeGen/R600/fcmp-cnd.ll | 2 +-
> test/CodeGen/R600/fcmp.ll | 5 +--
> test/CodeGen/R600/fdiv.ll | 14 ++++-----
> test/CodeGen/R600/floor.ll | 2 +-
> test/CodeGen/R600/fmad.ll | 2 +-
> test/CodeGen/R600/fmax.ll | 2 +-
> test/CodeGen/R600/fmin.ll | 2 +-
> test/CodeGen/R600/fmul.ll | 8 ++---
> test/CodeGen/R600/fmul.v4f32.ll | 6 ++--
> test/CodeGen/R600/fp_to_sint.ll | 8 ++---
> test/CodeGen/R600/fp_to_uint.ll | 8 ++---
> test/CodeGen/R600/fsub.ll | 8 ++---
> test/CodeGen/R600/i8-to-double-to-float.ll | 2 +-
> test/CodeGen/R600/icmp-select-sete-reverse-args.ll | 2 +-
> test/CodeGen/R600/literals.ll | 6 ++--
> test/CodeGen/R600/llvm.AMDGPU.mul.ll | 2 +-
> test/CodeGen/R600/llvm.AMDGPU.trunc.ll | 2 +-
> test/CodeGen/R600/llvm.cos.ll | 2 +-
> test/CodeGen/R600/llvm.pow.ll | 6 ++--
> test/CodeGen/R600/llvm.sin.ll | 2 +-
> test/CodeGen/R600/predicates.ll | 24 +++++++--------
> test/CodeGen/R600/reciprocal.ll | 2 +-
> test/CodeGen/R600/selectcc-cnd.ll | 3 +-
> test/CodeGen/R600/selectcc-cnde-int.ll | 3 +-
> test/CodeGen/R600/selectcc-icmp-select-float.ll | 3 +-
> test/CodeGen/R600/set-dx10.ll | 36 ++++++++++++++--------
> test/CodeGen/R600/sint_to_fp.ll | 8 ++---
> test/CodeGen/R600/uint_to_fp.ll | 8 ++---
> test/CodeGen/R600/unsupported-cc.ll | 24 ++++++++++-----
> 38 files changed, 172 insertions(+), 114 deletions(-)
>
> diff --git a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
> index 10547a5..5798ebb 100644
> --- a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
> +++ b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
> @@ -17,6 +17,7 @@ using namespace llvm;
>
> void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
> StringRef Annot) {
> + OS.flush();
Why did you add this?
> printInstruction(MI, OS);
>
> printAnnotation(OS, Annot);
> @@ -67,11 +68,14 @@ void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
> }
>
> void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
> - raw_ostream &O, StringRef Asm) {
> + raw_ostream &O, StringRef Asm,
> + StringRef Default) {
> const MCOperand &Op = MI->getOperand(OpNo);
> assert(Op.isImm());
> if (Op.getImm() == 1) {
> O << Asm;
> + } else {
> + O << Default;
> }
> }
>
> @@ -98,7 +102,7 @@ void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
>
> void AMDGPUInstPrinter::printLast(const MCInst *MI, unsigned OpNo,
> raw_ostream &O) {
> - printIfSet(MI, OpNo, O, " *");
> + printIfSet(MI, OpNo, O.indent(20 - O.GetNumBytesInBuffer()), "*", " ");
Can you explain exactly what you are doing here? I don't understand why
we are indenting.
> }
>
> void AMDGPUInstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
> @@ -169,4 +173,29 @@ void AMDGPUInstPrinter::printSel(const MCInst *MI, unsigned OpNo,
> O << "." << chans[chan];
> }
>
> +void AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
> + raw_ostream &O) {
> + int BankSwizzle = MI->getOperand(OpNo).getImm();
> + switch (BankSwizzle) {
> + case 1:
> + O << "BS:VEC_021";
> + break;
> + case 2:
> + O << "BS:VEC_120";
> + break;
> + case 3:
> + O << "BS:VEC_102";
> + break;
> + case 4:
> + O << "BS:VEC_201";
> + break;
> + case 5:
> + O << "BS:VEC_210";
> + break;
> + default:
> + break;
> + }
> + return;
> +}
> +
> #include "AMDGPUGenAsmWriter.inc"
> diff --git a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h
> index 767a708..65f808a 100644
> --- a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h
> +++ b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h
> @@ -35,7 +35,8 @@ private:
> void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
> void printInterpSlot(const MCInst *MI, unsigned OpNum, raw_ostream &O);
> void printMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
> - void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O, StringRef Asm);
> + void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O,
> + StringRef Asm, StringRef Default = "");
> void printAbs(const MCInst *MI, unsigned OpNo, raw_ostream &O);
> void printClamp(const MCInst *MI, unsigned OpNo, raw_ostream &O);
> void printLiteral(const MCInst *MI, unsigned OpNo, raw_ostream &O);
> @@ -47,6 +48,7 @@ private:
> void printUpdatePred(const MCInst *MI, unsigned OpNo, raw_ostream &O);
> void printWrite(const MCInst *MI, unsigned OpNo, raw_ostream &O);
> void printSel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
> + void printBankSwizzle(const MCInst *MI, unsigned OpNo, raw_ostream &O);
> };
>
> } // End namespace llvm
> diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td
> index 1d25da3..275794e 100644
> --- a/lib/Target/R600/R600Instructions.td
> +++ b/lib/Target/R600/R600Instructions.td
> @@ -78,7 +78,7 @@ def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))> {
> let PrintMethod = "printSel";
> }
> def BANK_SWIZZLE : OperandWithDefaultOps <i32, (ops (i32 0))> {
> - let PrintMethod = "printSel";
> + let PrintMethod = "printBankSwizzle";
> }
>
> def LITERAL : InstFlag<"printLiteral">;
> @@ -358,9 +358,9 @@ class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
> LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
> BANK_SWIZZLE:$bank_swizzle),
> !strconcat(" ", opName,
> - "$clamp $dst$write$dst_rel$omod, "
> + "$last$clamp $dst$write$dst_rel$omod, "
> "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
> - "$literal $pred_sel$last"),
> + "$pred_sel $bank_swizzle"),
Why did you change the position of the $last operand?
> pattern,
> itin>,
> R600ALU_Word0,
> @@ -399,10 +399,10 @@ class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
> LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
> BANK_SWIZZLE:$bank_swizzle),
> !strconcat(" ", opName,
> - "$clamp $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
> + "$last$clamp $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
> "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
> "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
> - "$literal $pred_sel$last"),
> + "$pred_sel $bank_swizzle"),
> pattern,
> itin>,
> R600ALU_Word0,
> @@ -436,11 +436,12 @@ class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
> R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel,
> LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
> BANK_SWIZZLE:$bank_swizzle),
> - !strconcat(" ", opName, "$clamp $dst$dst_rel, "
> + !strconcat(" ", opName, "$last$clamp $dst$dst_rel, "
> "$src0_neg$src0$src0_rel, "
> "$src1_neg$src1$src1_rel, "
> "$src2_neg$src2$src2_rel, "
> - "$literal $pred_sel$last"),
> + "$pred_sel"
> + "$bank_swizzle"),
> pattern,
> itin>,
> R600ALU_Word0,
> diff --git a/lib/Target/R600/R600RegisterInfo.td b/lib/Target/R600/R600RegisterInfo.td
> index 5a2e65c..bfc546b 100644
> --- a/lib/Target/R600/R600RegisterInfo.td
> +++ b/lib/Target/R600/R600RegisterInfo.td
> @@ -89,9 +89,9 @@ def ONE_INT : R600Reg<"1", 250>;
> def HALF : R600Reg<"0.5", 252>;
> def NEG_HALF : R600Reg<"-0.5", 252>;
> def ALU_LITERAL_X : R600RegWithChan<"literal.x", 253, "X">;
> -def ALU_LITERAL_Y : R600RegWithChan<"literal.x", 253, "Y">;
> -def ALU_LITERAL_Z : R600RegWithChan<"literal.x", 253, "Z">;
> -def ALU_LITERAL_W : R600RegWithChan<"literal.x", 253, "W">;
> +def ALU_LITERAL_Y : R600RegWithChan<"literal.y", 253, "Y">;
> +def ALU_LITERAL_Z : R600RegWithChan<"literal.z", 253, "Z">;
> +def ALU_LITERAL_W : R600RegWithChan<"literal.w", 253, "W">;
> def PV_X : R600RegWithChan<"PV.x", 254, "X">;
> def PV_Y : R600RegWithChan<"PV.y", 254, "Y">;
> def PV_Z : R600RegWithChan<"PV.z", 254, "Z">;
> diff --git a/test/CodeGen/R600/add.ll b/test/CodeGen/R600/add.ll
> index ac4a874..185998b 100644
> --- a/test/CodeGen/R600/add.ll
> +++ b/test/CodeGen/R600/add.ll
> @@ -1,9 +1,9 @@
> ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> ;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: ADD_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: ADD_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: ADD_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
I noticed this a few days ago, why doesn't the packetizer put these four
instructions in the same group?
> define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
> %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
> diff --git a/test/CodeGen/R600/and.ll b/test/CodeGen/R600/and.ll
> index 662085e..166af2d 100644
> --- a/test/CodeGen/R600/and.ll
> +++ b/test/CodeGen/R600/and.ll
> @@ -1,9 +1,9 @@
> ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> ;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
> %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
> diff --git a/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll b/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll
> index fd958b3..6607c12 100644
> --- a/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll
> +++ b/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll
> @@ -8,7 +8,7 @@
>
>
> ; CHECK: @sint
> -; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @sint(<4 x float> addrspace(1)* %out, i32 addrspace(1)* %in) {
> entry:
> @@ -22,7 +22,7 @@ entry:
> }
>
> ;CHECK: @uint
> -;CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @uint(<4 x float> addrspace(1)* %out, i32 addrspace(1)* %in) {
> entry:
> diff --git a/test/CodeGen/R600/fabs.ll b/test/CodeGen/R600/fabs.ll
> index 0407533..85f2882 100644
> --- a/test/CodeGen/R600/fabs.ll
> +++ b/test/CodeGen/R600/fabs.ll
> @@ -1,6 +1,6 @@
> ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> -;CHECK: MOV T{{[0-9]+\.[XYZW], \|T[0-9]+\.[XYZW]\|}}
> +;CHECK: MOV * T{{[0-9]+\.[XYZW], \|T[0-9]+\.[XYZW]\|}}
>
> define void @test() {
> %r0 = call float @llvm.R600.load.input(i32 0)
> diff --git a/test/CodeGen/R600/fadd.ll b/test/CodeGen/R600/fadd.ll
> index 81a4fa5..9a67232 100644
> --- a/test/CodeGen/R600/fadd.ll
> +++ b/test/CodeGen/R600/fadd.ll
> @@ -1,7 +1,7 @@
> ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> ; CHECK: @fadd_f32
> -; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @fadd_f32() {
> %r0 = call float @llvm.R600.load.input(i32 0)
> @@ -17,9 +17,9 @@ declare void @llvm.AMDGPU.store.output(float, i32)
>
> ; CHECK: @fadd_v4f32
> ; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @fadd_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
> %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
> diff --git a/test/CodeGen/R600/fcmp-cnd.ll b/test/CodeGen/R600/fcmp-cnd.ll
> index a94cfb5..7373a21 100644
> --- a/test/CodeGen/R600/fcmp-cnd.ll
> +++ b/test/CodeGen/R600/fcmp-cnd.ll
> @@ -2,7 +2,7 @@
>
> ;Not checking arguments 2 and 3 to CNDE, because they may change between
> ;registers and literal.x depending on what the optimizer does.
> -;CHECK: CNDE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: CNDE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @test(i32 addrspace(1)* %out, float addrspace(1)* %in) {
> entry:
> diff --git a/test/CodeGen/R600/fcmp.ll b/test/CodeGen/R600/fcmp.ll
> index 37f621d..dc3a779 100644
> --- a/test/CodeGen/R600/fcmp.ll
> +++ b/test/CodeGen/R600/fcmp.ll
> @@ -1,7 +1,7 @@
> ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> ; CHECK: @fcmp_sext
> -; CHECK: SETE_DX10 T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: SETE_DX10 * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @fcmp_sext(i32 addrspace(1)* %out, float addrspace(1)* %in) {
> entry:
> @@ -19,7 +19,8 @@ entry:
> ; SET* + FP_TO_SINT
>
> ; CHECK: @fcmp_br
> -; CHECK: SET{{[N]*}}E_DX10 T{{[0-9]+\.[XYZW], [a-zA-Z0-9, .]+}}(5.0
> +; CHECK: SET{{[N]*}}E_DX10 * T{{[0-9]+\.[XYZW],}}
> +; CHECK-NEXT {{[0-9]+(5.0}}
>
> define void @fcmp_br(i32 addrspace(1)* %out, float %in) {
> entry:
> diff --git a/test/CodeGen/R600/fdiv.ll b/test/CodeGen/R600/fdiv.ll
> index 79e677f..2e68e36 100644
> --- a/test/CodeGen/R600/fdiv.ll
> +++ b/test/CodeGen/R600/fdiv.ll
> @@ -1,13 +1,13 @@
> ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> -;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> ;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
> %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
> diff --git a/test/CodeGen/R600/floor.ll b/test/CodeGen/R600/floor.ll
> index 845330f..877d69a 100644
> --- a/test/CodeGen/R600/floor.ll
> +++ b/test/CodeGen/R600/floor.ll
> @@ -1,6 +1,6 @@
> ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> -;CHECK: FLOOR T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: FLOOR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @test() {
> %r0 = call float @llvm.R600.load.input(i32 0)
> diff --git a/test/CodeGen/R600/fmad.ll b/test/CodeGen/R600/fmad.ll
> index a3d4d0f..62001ed 100644
> --- a/test/CodeGen/R600/fmad.ll
> +++ b/test/CodeGen/R600/fmad.ll
> @@ -1,6 +1,6 @@
> ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> -;CHECK: MULADD_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: MULADD_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @test() {
> %r0 = call float @llvm.R600.load.input(i32 0)
> diff --git a/test/CodeGen/R600/fmax.ll b/test/CodeGen/R600/fmax.ll
> index 3708f0b..8b704e5 100644
> --- a/test/CodeGen/R600/fmax.ll
> +++ b/test/CodeGen/R600/fmax.ll
> @@ -1,6 +1,6 @@
> ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> -;CHECK: MAX T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: MAX * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @test() {
> %r0 = call float @llvm.R600.load.input(i32 0)
> diff --git a/test/CodeGen/R600/fmin.ll b/test/CodeGen/R600/fmin.ll
> index 19d59ab..5e34b7c 100644
> --- a/test/CodeGen/R600/fmin.ll
> +++ b/test/CodeGen/R600/fmin.ll
> @@ -1,6 +1,6 @@
> ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> -;CHECK: MIN T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: MIN * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @test() {
> %r0 = call float @llvm.R600.load.input(i32 0)
> diff --git a/test/CodeGen/R600/fmul.ll b/test/CodeGen/R600/fmul.ll
> index 7fd22d8..c292946 100644
> --- a/test/CodeGen/R600/fmul.ll
> +++ b/test/CodeGen/R600/fmul.ll
> @@ -1,7 +1,7 @@
> ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> ; CHECK: @fmul_f32
> -; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @fmul_f32() {
> %r0 = call float @llvm.R600.load.input(i32 0)
> @@ -17,9 +17,9 @@ declare void @llvm.AMDGPU.store.output(float, i32)
>
> ; CHECK: @fmul_v4f32
> ; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
> %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
> diff --git a/test/CodeGen/R600/fmul.v4f32.ll b/test/CodeGen/R600/fmul.v4f32.ll
> index 6d44a0c..74a58f7 100644
> --- a/test/CodeGen/R600/fmul.v4f32.ll
> +++ b/test/CodeGen/R600/fmul.v4f32.ll
> @@ -1,9 +1,9 @@
> ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> ;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
> %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
> diff --git a/test/CodeGen/R600/fp_to_sint.ll b/test/CodeGen/R600/fp_to_sint.ll
> index 9c21ad2..f5716e1 100644
> --- a/test/CodeGen/R600/fp_to_sint.ll
> +++ b/test/CodeGen/R600/fp_to_sint.ll
> @@ -1,10 +1,10 @@
> ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> ; CHECK: @fp_to_sint_v4i32
> -; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: FLT_TO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: FLT_TO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: FLT_TO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: FLT_TO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @fp_to_sint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
> %value = load <4 x float> addrspace(1) * %in
> diff --git a/test/CodeGen/R600/fp_to_uint.ll b/test/CodeGen/R600/fp_to_uint.ll
> index d91098f..1c3c0c6 100644
> --- a/test/CodeGen/R600/fp_to_uint.ll
> +++ b/test/CodeGen/R600/fp_to_uint.ll
> @@ -1,10 +1,10 @@
> ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> ; CHECK: @fp_to_uint_v4i32
> -; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @fp_to_uint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
> %value = load <4 x float> addrspace(1) * %in
> diff --git a/test/CodeGen/R600/fsub.ll b/test/CodeGen/R600/fsub.ll
> index 812388b..f784cde 100644
> --- a/test/CodeGen/R600/fsub.ll
> +++ b/test/CodeGen/R600/fsub.ll
> @@ -1,7 +1,7 @@
> ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> ; CHECK: @fsub_f32
> -; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
> +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
>
> define void @fsub_f32() {
> %r0 = call float @llvm.R600.load.input(i32 0)
> @@ -17,9 +17,9 @@ declare void @llvm.AMDGPU.store.output(float, i32)
>
> ; CHECK: @fsub_v4f32
> ; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
> %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
> diff --git a/test/CodeGen/R600/i8-to-double-to-float.ll b/test/CodeGen/R600/i8-to-double-to-float.ll
> index 39f3322..6047466 100644
> --- a/test/CodeGen/R600/i8-to-double-to-float.ll
> +++ b/test/CodeGen/R600/i8-to-double-to-float.ll
> @@ -1,6 +1,6 @@
> ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> -;CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @test(float addrspace(1)* %out, i8 addrspace(1)* %in) {
> %1 = load i8 addrspace(1)* %in
> diff --git a/test/CodeGen/R600/icmp-select-sete-reverse-args.ll b/test/CodeGen/R600/icmp-select-sete-reverse-args.ll
> index 71705a6..e3005fe 100644
> --- a/test/CodeGen/R600/icmp-select-sete-reverse-args.ll
> +++ b/test/CodeGen/R600/icmp-select-sete-reverse-args.ll
> @@ -3,7 +3,7 @@
> ;Test that a select with reversed True/False values is correctly lowered
> ;to a SETNE_INT. There should only be one SETNE_INT instruction.
>
> -;CHECK: SETNE_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: SETNE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> ;CHECK-NOT: SETNE_INT
>
> define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
> diff --git a/test/CodeGen/R600/literals.ll b/test/CodeGen/R600/literals.ll
> index e69f64e..5e400a7 100644
> --- a/test/CodeGen/R600/literals.ll
> +++ b/test/CodeGen/R600/literals.ll
> @@ -7,7 +7,8 @@
> ; ADD_INT literal.x REG, 5
>
> ; CHECK: @i32_literal
> -; CHECK: ADD_INT {{[A-Z0-9,. ]*}}literal.x,{{[A-Z0-9,. ]*}} 5
> +; CHECK: ADD_INT * {{[A-Z0-9,. ]*}}literal.x
> +; CHECK-NEXT: 5
> define void @i32_literal(i32 addrspace(1)* %out, i32 %in) {
> entry:
> %0 = add i32 5, %in
> @@ -22,7 +23,8 @@ entry:
> ; ADD literal.x REG, 5.0
>
> ; CHECK: @float_literal
> -; CHECK: ADD {{[A-Z0-9,. ]*}}literal.x,{{[A-Z0-9,. ]*}} {{[0-9]+}}(5.0
> +; CHECK: ADD * {{[A-Z0-9,. ]*}}literal.x
> +; CHECK-NEXT: 1084227584(5.0
> define void @float_literal(float addrspace(1)* %out, float %in) {
> entry:
> %0 = fadd float 5.0, %in
> diff --git a/test/CodeGen/R600/llvm.AMDGPU.mul.ll b/test/CodeGen/R600/llvm.AMDGPU.mul.ll
> index 693eb27..cc0732b 100644
> --- a/test/CodeGen/R600/llvm.AMDGPU.mul.ll
> +++ b/test/CodeGen/R600/llvm.AMDGPU.mul.ll
> @@ -1,6 +1,6 @@
> ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> -;CHECK: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @test() {
> %r0 = call float @llvm.R600.load.input(i32 0)
> diff --git a/test/CodeGen/R600/llvm.AMDGPU.trunc.ll b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll
> index fac957f..ff22a69 100644
> --- a/test/CodeGen/R600/llvm.AMDGPU.trunc.ll
> +++ b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll
> @@ -1,6 +1,6 @@
> ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> -;CHECK: TRUNC T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: TRUNC * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @test() {
> %r0 = call float @llvm.R600.load.input(i32 0)
> diff --git a/test/CodeGen/R600/llvm.cos.ll b/test/CodeGen/R600/llvm.cos.ll
> index dc120bf..9b28167 100644
> --- a/test/CodeGen/R600/llvm.cos.ll
> +++ b/test/CodeGen/R600/llvm.cos.ll
> @@ -1,6 +1,6 @@
> ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> -;CHECK: COS T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: COS * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @test() {
> %r0 = call float @llvm.R600.load.input(i32 0)
> diff --git a/test/CodeGen/R600/llvm.pow.ll b/test/CodeGen/R600/llvm.pow.ll
> index b4ce9f4..91b7742 100644
> --- a/test/CodeGen/R600/llvm.pow.ll
> +++ b/test/CodeGen/R600/llvm.pow.ll
> @@ -1,8 +1,8 @@
> ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> -;CHECK: LOG_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -;CHECK-NEXT: EXP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK-NEXT: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @test() {
> %r0 = call float @llvm.R600.load.input(i32 0)
> diff --git a/test/CodeGen/R600/llvm.sin.ll b/test/CodeGen/R600/llvm.sin.ll
> index 5cd6998..803dc2d 100644
> --- a/test/CodeGen/R600/llvm.sin.ll
> +++ b/test/CodeGen/R600/llvm.sin.ll
> @@ -1,6 +1,6 @@
> ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> -;CHECK: SIN T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: SIN * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @test() {
> %r0 = call float @llvm.R600.load.input(i32 0)
> diff --git a/test/CodeGen/R600/predicates.ll b/test/CodeGen/R600/predicates.ll
> index fb093ed..0d3eeef 100644
> --- a/test/CodeGen/R600/predicates.ll
> +++ b/test/CodeGen/R600/predicates.ll
> @@ -4,8 +4,8 @@
> ; when it is legal to do so.
>
> ; CHECK: @simple_if
> -; CHECK: PRED_SET{{[EGN][ET]*}}_INT Pred,
> -; CHECK: LSHL T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, 0(0.000000e+00) Pred_sel
> +; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred,
> +; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
> define void @simple_if(i32 addrspace(1)* %out, i32 %in) {
> entry:
> %0 = icmp sgt i32 %in, 0
> @@ -22,9 +22,9 @@ ENDIF:
> }
>
> ; CHECK: @simple_if_else
> -; CHECK: PRED_SET{{[EGN][ET]*}}_INT Pred,
> -; CHECK: LSH{{[LR] T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, 0(0.000000e+00) Pred_sel
> -; CHECK: LSH{{[LR] T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, 0(0.000000e+00) Pred_sel
> +; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred,
> +; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
> +; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
> define void @simple_if_else(i32 addrspace(1)* %out, i32 %in) {
> entry:
> %0 = icmp sgt i32 %in, 0
> @@ -48,9 +48,9 @@ ENDIF:
> ; CHECK: ALU_PUSH_BEFORE
> ; CHECK: JUMP
> ; CHECK: POP
> -; CHECK: PRED_SET{{[EGN][ET]*}}_INT Exec
> -; CHECK: PRED_SET{{[EGN][ET]*}}_INT Pred,
> -; CHECK: LSHL T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, 0(0.000000e+00) Pred_sel
> +; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Exec
> +; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred,
> +; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
> define void @nested_if(i32 addrspace(1)* %out, i32 %in) {
> entry:
> %0 = icmp sgt i32 %in, 0
> @@ -75,10 +75,10 @@ ENDIF:
> ; CHECK: ALU_PUSH_BEFORE
> ; CHECK: JUMP
> ; CHECK: POP
> -; CHECK: PRED_SET{{[EGN][ET]*}}_INT Exec
> -; CHECK: PRED_SET{{[EGN][ET]*}}_INT Pred,
> -; CHECK: LSH{{[LR] T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, 0(0.000000e+00) Pred_sel
> -; CHECK: LSH{{[LR] T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, 0(0.000000e+00) Pred_sel
> +; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Exec
> +; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred,
> +; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
> +; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
> define void @nested_if_else(i32 addrspace(1)* %out, i32 %in) {
> entry:
> %0 = icmp sgt i32 %in, 0
> diff --git a/test/CodeGen/R600/reciprocal.ll b/test/CodeGen/R600/reciprocal.ll
> index 6838c1a..2783929 100644
> --- a/test/CodeGen/R600/reciprocal.ll
> +++ b/test/CodeGen/R600/reciprocal.ll
> @@ -1,6 +1,6 @@
> ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> -;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @test() {
> %r0 = call float @llvm.R600.load.input(i32 0)
> diff --git a/test/CodeGen/R600/selectcc-cnd.ll b/test/CodeGen/R600/selectcc-cnd.ll
> index f0a0f51..d7287b4 100644
> --- a/test/CodeGen/R600/selectcc-cnd.ll
> +++ b/test/CodeGen/R600/selectcc-cnd.ll
> @@ -1,7 +1,8 @@
> ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> ;CHECK-NOT: SETE
> -;CHECK: CNDE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], 1.0, literal.x, [-0-9]+\(2.0}}
> +;CHECK: CNDE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1.0, literal.x,
> +;CHECK-NEXT: {{[-0-9]+\(2.0}}
> define void @test(float addrspace(1)* %out, float addrspace(1)* %in) {
> %1 = load float addrspace(1)* %in
> %2 = fcmp oeq float %1, 0.0
> diff --git a/test/CodeGen/R600/selectcc-cnde-int.ll b/test/CodeGen/R600/selectcc-cnde-int.ll
> index b38078e..768dc7d 100644
> --- a/test/CodeGen/R600/selectcc-cnde-int.ll
> +++ b/test/CodeGen/R600/selectcc-cnde-int.ll
> @@ -1,7 +1,8 @@
> ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> ;CHECK-NOT: SETE_INT
> -;CHECK: CNDE_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], 1, literal.x, 2}}
> +;CHECK: CNDE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, literal.x,
> +;CHECK-NEXT: 2
> define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
> %1 = load i32 addrspace(1)* %in
> %2 = icmp eq i32 %1, 0
> diff --git a/test/CodeGen/R600/selectcc-icmp-select-float.ll b/test/CodeGen/R600/selectcc-icmp-select-float.ll
> index 359ca1e..6743800 100644
> --- a/test/CodeGen/R600/selectcc-icmp-select-float.ll
> +++ b/test/CodeGen/R600/selectcc-icmp-select-float.ll
> @@ -2,7 +2,8 @@
>
> ; Note additional optimizations may cause this SGT to be replaced with a
> ; CND* instruction.
> -; CHECK: SETGT_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], literal.x, -1}}
> +; CHECK: SETGT_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, literal.x,
> +; CHECK-NEXT: -1
> ; Test a selectcc with i32 LHS/RHS and float True/False
>
> define void @test(float addrspace(1)* %out, i32 addrspace(1)* %in) {
> diff --git a/test/CodeGen/R600/set-dx10.ll b/test/CodeGen/R600/set-dx10.ll
> index 54febcf..eb6e9d2 100644
> --- a/test/CodeGen/R600/set-dx10.ll
> +++ b/test/CodeGen/R600/set-dx10.ll
> @@ -5,7 +5,8 @@
> ; SET*DX10 instructions.
>
> ; CHECK: @fcmp_une_select_fptosi
> -; CHECK: SETNE_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00)
> +; CHECK: SETNE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x,
> +; CHECK-NEXT: 1084227584(5.000000e+00)
> define void @fcmp_une_select_fptosi(i32 addrspace(1)* %out, float %in) {
> entry:
> %0 = fcmp une float %in, 5.0
> @@ -17,7 +18,8 @@ entry:
> }
>
> ; CHECK: @fcmp_une_select_i32
> -; CHECK: SETNE_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00)
> +; CHECK: SETNE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x,
> +; CHECK-NEXT: 1084227584(5.000000e+00)
> define void @fcmp_une_select_i32(i32 addrspace(1)* %out, float %in) {
> entry:
> %0 = fcmp une float %in, 5.0
> @@ -27,7 +29,8 @@ entry:
> }
>
> ; CHECK: @fcmp_ueq_select_fptosi
> -; CHECK: SETE_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00)
> +; CHECK: SETE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x,
> +; CHECK-NEXT: 1084227584(5.000000e+00)
> define void @fcmp_ueq_select_fptosi(i32 addrspace(1)* %out, float %in) {
> entry:
> %0 = fcmp ueq float %in, 5.0
> @@ -39,7 +42,8 @@ entry:
> }
>
> ; CHECK: @fcmp_ueq_select_i32
> -; CHECK: SETE_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00)
> +; CHECK: SETE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x,
> +; CHECK-NEXT: 1084227584(5.000000e+00)
> define void @fcmp_ueq_select_i32(i32 addrspace(1)* %out, float %in) {
> entry:
> %0 = fcmp ueq float %in, 5.0
> @@ -49,7 +53,8 @@ entry:
> }
>
> ; CHECK: @fcmp_ugt_select_fptosi
> -; CHECK: SETGT_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00)
> +; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x,
> +; CHECK-NEXT: 1084227584(5.000000e+00)
> define void @fcmp_ugt_select_fptosi(i32 addrspace(1)* %out, float %in) {
> entry:
> %0 = fcmp ugt float %in, 5.0
> @@ -61,7 +66,8 @@ entry:
> }
>
> ; CHECK: @fcmp_ugt_select_i32
> -; CHECK: SETGT_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00)
> +; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x,
> +; CHECK-NEXT: 1084227584(5.000000e+00)
> define void @fcmp_ugt_select_i32(i32 addrspace(1)* %out, float %in) {
> entry:
> %0 = fcmp ugt float %in, 5.0
> @@ -71,7 +77,8 @@ entry:
> }
>
> ; CHECK: @fcmp_uge_select_fptosi
> -; CHECK: SETGE_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00)
> +; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x,
> +; CHECK-NEXT: 1084227584(5.000000e+00)
> define void @fcmp_uge_select_fptosi(i32 addrspace(1)* %out, float %in) {
> entry:
> %0 = fcmp uge float %in, 5.0
> @@ -83,7 +90,8 @@ entry:
> }
>
> ; CHECK: @fcmp_uge_select_i32
> -; CHECK: SETGE_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00)
> +; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x,
> +; CHECK-NEXT: 1084227584(5.000000e+00)
> define void @fcmp_uge_select_i32(i32 addrspace(1)* %out, float %in) {
> entry:
> %0 = fcmp uge float %in, 5.0
> @@ -93,7 +101,8 @@ entry:
> }
>
> ; CHECK: @fcmp_ule_select_fptosi
> -; CHECK: SETGE_DX10 T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00)
> +; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}},
> +; CHECK-NEXT: 1084227584(5.000000e+00)
> define void @fcmp_ule_select_fptosi(i32 addrspace(1)* %out, float %in) {
> entry:
> %0 = fcmp ule float %in, 5.0
> @@ -105,7 +114,8 @@ entry:
> }
>
> ; CHECK: @fcmp_ule_select_i32
> -; CHECK: SETGE_DX10 T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00)
> +; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}},
> +; CHECK-NEXT: 1084227584(5.000000e+00)
> define void @fcmp_ule_select_i32(i32 addrspace(1)* %out, float %in) {
> entry:
> %0 = fcmp ule float %in, 5.0
> @@ -115,7 +125,8 @@ entry:
> }
>
> ; CHECK: @fcmp_ult_select_fptosi
> -; CHECK: SETGT_DX10 T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00)
> +; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}},
> +; CHECK-NEXT: 1084227584(5.000000e+00)
> define void @fcmp_ult_select_fptosi(i32 addrspace(1)* %out, float %in) {
> entry:
> %0 = fcmp ult float %in, 5.0
> @@ -127,7 +138,8 @@ entry:
> }
>
> ; CHECK: @fcmp_ult_select_i32
> -; CHECK: SETGT_DX10 T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00)
> +; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}},
> +; CHECK-NEXT: 1084227584(5.000000e+00)
> define void @fcmp_ult_select_i32(i32 addrspace(1)* %out, float %in) {
> entry:
> %0 = fcmp ult float %in, 5.0
> diff --git a/test/CodeGen/R600/sint_to_fp.ll b/test/CodeGen/R600/sint_to_fp.ll
> index 6a56db3..91a8eb7 100644
> --- a/test/CodeGen/R600/sint_to_fp.ll
> +++ b/test/CodeGen/R600/sint_to_fp.ll
> @@ -1,10 +1,10 @@
> ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> ; CHECK: @sint_to_fp_v4i32
> -; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @sint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
> %value = load <4 x i32> addrspace(1) * %in
> diff --git a/test/CodeGen/R600/uint_to_fp.ll b/test/CodeGen/R600/uint_to_fp.ll
> index ae8fc8e..9054fc4 100644
> --- a/test/CodeGen/R600/uint_to_fp.ll
> +++ b/test/CodeGen/R600/uint_to_fp.ll
> @@ -1,10 +1,10 @@
> ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> ; CHECK: @uint_to_fp_v4i32
> -; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> -; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +; CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> define void @uint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
> %value = load <4 x i32> addrspace(1) * %in
> diff --git a/test/CodeGen/R600/unsupported-cc.ll b/test/CodeGen/R600/unsupported-cc.ll
> index b48c591..b311f4c 100644
> --- a/test/CodeGen/R600/unsupported-cc.ll
> +++ b/test/CodeGen/R600/unsupported-cc.ll
> @@ -3,7 +3,8 @@
> ; These tests are for condition codes that are not supported by the hardware
>
> ; CHECK: @slt
> -; CHECK: SETGT_INT T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, 5(7.006492e-45)
> +; CHECK: SETGT_INT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}},
> +; CHECK-NEXT: 5(7.006492e-45)
> define void @slt(i32 addrspace(1)* %out, i32 %in) {
> entry:
> %0 = icmp slt i32 %in, 5
> @@ -13,7 +14,8 @@ entry:
> }
>
> ; CHECK: @ult_i32
> -; CHECK: SETGT_UINT T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, 5(7.006492e-45)
> +; CHECK: SETGT_UINT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}},
> +; CHECK-NEXT: 5(7.006492e-45)
> define void @ult_i32(i32 addrspace(1)* %out, i32 %in) {
> entry:
> %0 = icmp ult i32 %in, 5
> @@ -23,7 +25,8 @@ entry:
> }
>
> ; CHECK: @ult_float
> -; CHECK: SETGT T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00)
> +; CHECK: SETGT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}},
> +; CHECK-NEXT: 1084227584(5.000000e+00)
> define void @ult_float(float addrspace(1)* %out, float %in) {
> entry:
> %0 = fcmp ult float %in, 5.0
> @@ -33,7 +36,8 @@ entry:
> }
>
> ; CHECK: @olt
> -; CHECK: SETGT T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00)
> +; CHECK: SETGT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}},
> +;CHECK-NEXT: 1084227584(5.000000e+00)
> define void @olt(float addrspace(1)* %out, float %in) {
> entry:
> %0 = fcmp olt float %in, 5.0
> @@ -43,7 +47,8 @@ entry:
> }
>
> ; CHECK: @sle
> -; CHECK: SETGT_INT T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, 6(8.407791e-45)
> +; CHECK: SETGT_INT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}},
> +; CHECK-NEXT: 6(8.407791e-45)
> define void @sle(i32 addrspace(1)* %out, i32 %in) {
> entry:
> %0 = icmp sle i32 %in, 5
> @@ -53,7 +58,8 @@ entry:
> }
>
> ; CHECK: @ule_i32
> -; CHECK: SETGT_UINT T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, 6(8.407791e-45)
> +; CHECK: SETGT_UINT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}},
> +; CHECK-NEXT: 6(8.407791e-45)
> define void @ule_i32(i32 addrspace(1)* %out, i32 %in) {
> entry:
> %0 = icmp ule i32 %in, 5
> @@ -63,7 +69,8 @@ entry:
> }
>
> ; CHECK: @ule_float
> -; CHECK: SETGE T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00)
> +; CHECK: SETGE * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}},
> +; CHECK-NEXT: 1084227584(5.000000e+00)
> define void @ule_float(float addrspace(1)* %out, float %in) {
> entry:
> %0 = fcmp ule float %in, 5.0
> @@ -73,7 +80,8 @@ entry:
> }
>
> ; CHECK: @ole
> -; CHECK: SETGE T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00)
> +; CHECK: SETGE * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}},
> +; CHECK-NEXT:1084227584(5.000000e+00)
> define void @ole(float addrspace(1)* %out, float %in) {
> entry:
> %0 = fcmp ole float %in, 5.0
> --
> 1.8.1.4
>
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