[PATCH] Filter out Pseudo nodes in ScheduleDAGVLIW

[Andrew Trick]

On Apr 30, 2013, at 10:04 AM, Sergei Larin <slarin at codeaurora.org> wrote:

> Stefan,
> 
> This looks good to me, but please wait for OK from Andy.

LGTM. Thanks.
-Andy

> ---
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
> The Linux Foundation
> 
> 
>> -----Original Message-----
>> From: Stefan Hepp [mailto:stefan at stefant.org]
>> Sent: Tuesday, April 30, 2013 7:52 AM
>> To: Sergei Larin
>> Cc: llvm-commits at cs.uiuc.edu
>> Subject: Re: [PATCH] Filter out Pseudo nodes in ScheduleDAGVLIW
>> 
>> Hi Sergei,
>> 
>> On 04/29/2013 11:30 PM, Sergei Larin wrote:
>>>   Would you happen to have a test case for this? Thanks.
>> 
>> The SDNodes that caused the problems for me are the INLINEASM and
>> COPY_TO_REGCLASS nodes, which trigger the assertions in the
>> HazardRecognizer and PriorityQueue. However, I cannot reproduce this in
>> the Hexagon backend, so obviously those nodes are handled somehow
>> differently there, though I have not been able to find out how (it is
>> not due to InlineAsm being a schedule boundary, at least)..
>> 
>> So the only 'testcase' I have is our backend itself.. it is available
>> on github
>> (https://github.com/t-crest/patmos-llvm/tree/master/lib/Target/Patmos)
>> if you *really* want to look into it, but apart from that I have to say
>> I have no test case that triggers the problem in the mainstream
>> backends.
>> 
>> I am also not sure whether the correct way of addressing this is
>> skipping the pseudo nodes in the ScheduleDAG (like the RRList
>> scheduler) or not letting those nodes reach the VLIW scheduler in the
>> first place, like Hexagon seems to manage to do. The first way of doing
>> it seems more robust and should allow the packetizer to reset its state
>> when encountering inline assembly though (as far as I understand it,
>> assuming that it is not the DFAPacketizer that actually filters out
>> inline-asm nodes in Hexagon..).
>> 
>> Kind regards,
>>  Stefan
>> 
>> 
>>>> -----Original Message-----
>>>> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-
>>>> bounces at cs.uiuc.edu] On Behalf Of Stefan Hepp
>>>> Sent: Monday, April 29, 2013 7:54 AM
>>>> To: llvm-commits at cs.uiuc.edu
>>>> Subject: [PATCH] Filter out Pseudo nodes in ScheduleDAGVLIW
>>>> 
>>>> Hi,
>>>> 
>>>> ScheduleDAGVLIW uses the HazardRecognizer, but does not filter out
>>>> any Pseudo nodes, causing the ScoreboardHazardRecognizer to run into
>>>> an
>>>> assertion:
>>>> 
>>>> virtual void
>>>> llvm::ScoreboardHazardRecognizer::EmitInstruction(llvm::SUnit *):
>>>> Assertion `MCID && "The scheduler must filter non-machineinstrs"'
>>>> failed.
>>>> 
>>>> I copied the EmitNode function from ScheduleDAGRRList which does
>>>> exactly that and added it to ScheduleDAGVLIW, and filtered out
>>>> COPY_TO_REGCLASS in the ResourcePriorityQueue, now the VLIW
>> scheduler
>>>> also works for my custom backend (and the llvm tests still work).
>>>> 
>>>> I attached the patch to this email. It is against LLVM 3.2, but the
>>>> relevant code has not changed in upstream.
>>>> 
>>>> Regards,
>>>>   Stefan

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