[llvm] r180778 - s tightens up the encoding description for ARM post-indexed ldr instructions. All instructions in this class have bit 4 cleared. It turns out that there is a test case for this, but it was marked XFAIL.

[Mihai Popa]

Author: mpopa
Date: Tue Apr 30 04:00:12 2013
New Revision: 180778

URL: http://llvm.org/viewvc/llvm-project?rev=180778&view=rev
Log:
s tightens up the encoding description for ARM post-indexed ldr instructions. All instructions in this class have bit 4 cleared. It turns out that there is a test case for this, but it was marked XFAIL.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=180778&r1=180777&r2=180778&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Apr 30 04:00:12 2013
@@ -2313,6 +2313,7 @@ multiclass AI2_ldridx<bit isByte, string
      let Inst{23} = offset{12};
      let Inst{19-16} = addr;
      let Inst{11-0} = offset{11-0};
+     let Inst{4} = 0;
 
     let DecoderMethod = "DecodeAddrMode2IdxInstruction";
    }

Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt?rev=180778&r1=180777&r2=180778&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt Tue Apr 30 04:00:12 2013
@@ -1,5 +1,4 @@
 # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-# XFAIL: *
 
 # LDR_PRE/POST has encoding Inst{4} = 0.
 0xde 0x69 0x18 0x46