[llvm] r180039 - [mips] In performDSPShiftCombine, check that all elements in the vector are

[Akira Hatanaka]

Author: ahatanak
Date: Mon Apr 22 14:58:23 2013
New Revision: 180039

URL: http://llvm.org/viewvc/llvm-project?rev=180039&view=rev
Log:
[mips] In performDSPShiftCombine, check that all elements in the vector are
shifted by the same amount and the shift amount is smaller than the element
size.


Modified:
    llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td
    llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
    llvm/trunk/test/CodeGen/Mips/dsp-patterns.ll

Modified: llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td?rev=180039&r1=180038&r2=180039&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td Mon Apr 22 14:58:23 2013
@@ -1288,18 +1288,18 @@ def : DSPBinPat<ADDWC, i32, adde>;
 
 // Shift immediate patterns.
 class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
-                  ImmLeaf Imm, Predicate Pred = HasDSP> :
+                  SDPatternOperator Imm, Predicate Pred = HasDSP> :
   DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
 
-def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, immZExt4>;
-def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, immZExt4>;
-def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, immZExt4, HasDSPR2>;
+def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>;
+def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>;
+def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>;
 def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>;
 def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>;
 def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>;
-def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, immZExt3>;
-def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, immZExt3, HasDSPR2>;
-def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, immZExt3>;
+def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;
+def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>;
+def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>;
 def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;
 def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;
 def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;

Modified: llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp?rev=180039&r1=180038&r2=180039&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp Mon Apr 22 14:58:23 2013
@@ -327,9 +327,11 @@ static SDValue performDSPShiftCombine(un
   unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
   BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
 
-  if (!BV || !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
-                                  HasAnyUndefs, EltSize,
-                                  !Subtarget->isLittle()))
+  if (!BV ||
+      !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, EltSize,
+                           !Subtarget->isLittle()) ||
+      (SplatBitSize != EltSize) ||
+      !isUIntN(Log2_32(EltSize), SplatValue.getZExtValue()))
     return SDValue();
 
   return DAG.getNode(Opc, N->getDebugLoc(), Ty, N->getOperand(0),

Modified: llvm/trunk/test/CodeGen/Mips/dsp-patterns.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/dsp-patterns.ll?rev=180039&r1=180038&r2=180039&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/dsp-patterns.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/dsp-patterns.ll Mon Apr 22 14:58:23 2013
@@ -203,3 +203,59 @@ entry:
   %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
   ret { i32 } %.fca.0.insert
 }
+
+; Check that shift node is expanded if splat element size is not 16-bit.
+;
+; R1: test_vector_splat_imm_v2q15:
+; R1-NOT: shll.ph
+
+define { i32 } @test_vector_splat_imm_v2q15(i32 %a.coerce) {
+entry:
+  %0 = bitcast i32 %a.coerce to <2 x i16>
+  %shl = shl <2 x i16> %0, <i16 0, i16 2>
+  %1 = bitcast <2 x i16> %shl to i32
+  %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
+  ret { i32 } %.fca.0.insert
+}
+
+; Check that shift node is expanded if splat element size is not 8-bit.
+;
+; R1: test_vector_splat_imm_v4i8:
+; R1-NOT: shll.qb
+
+define { i32 } @test_vector_splat_imm_v4i8(i32 %a.coerce) {
+entry:
+  %0 = bitcast i32 %a.coerce to <4 x i8>
+  %shl = shl <4 x i8> %0, <i8 0, i8 2, i8 0, i8 2>
+  %1 = bitcast <4 x i8> %shl to i32
+  %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
+  ret { i32 } %.fca.0.insert
+}
+
+; Check that shift node is expanded if shift amount doesn't fit in 4-bit sa field.
+;
+; R1: test_shift_amount_v2q15:
+; R1-NOT: shll.ph
+
+define { i32 } @test_shift_amount_v2q15(i32 %a.coerce) {
+entry:
+  %0 = bitcast i32 %a.coerce to <2 x i16>
+  %shl = shl <2 x i16> %0, <i16 16, i16 16>
+  %1 = bitcast <2 x i16> %shl to i32
+  %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
+  ret { i32 } %.fca.0.insert
+}
+
+; Check that shift node is expanded if shift amount doesn't fit in 3-bit sa field.
+;
+; R1: test_shift_amount_v4i8:
+; R1-NOT: shll.qb
+
+define { i32 } @test_shift_amount_v4i8(i32 %a.coerce) {
+entry:
+  %0 = bitcast i32 %a.coerce to <4 x i8>
+  %shl = shl <4 x i8> %0, <i8 8, i8 8, i8 8, i8 8>
+  %1 = bitcast <4 x i8> %shl to i32
+  %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
+  ret { i32 } %.fca.0.insert
+}