[llvm] r179828 - R600: Reorganize lit tests and document how they should be organized
Tom Stellard
thomas.stellard at amd.com
Thu Apr 18 19:10:54 PDT 2013
Author: tstellar
Date: Thu Apr 18 21:10:53 2013
New Revision: 179828
URL: http://llvm.org/viewvc/llvm-project?rev=179828&view=rev
Log:
R600: Reorganize lit tests and document how they should be organized
Added:
llvm/trunk/test/CodeGen/R600/README
llvm/trunk/test/CodeGen/R600/add.ll
- copied, changed from r179820, llvm/trunk/test/CodeGen/R600/add.v4i32.ll
llvm/trunk/test/CodeGen/R600/and.ll
- copied, changed from r179820, llvm/trunk/test/CodeGen/R600/and.v4i32.ll
llvm/trunk/test/CodeGen/R600/fdiv.ll
- copied, changed from r179820, llvm/trunk/test/CodeGen/R600/fdiv.v4f32.ll
llvm/trunk/test/CodeGen/R600/fp_to_sint.ll
llvm/trunk/test/CodeGen/R600/fp_to_uint.ll
llvm/trunk/test/CodeGen/R600/i8-to-double-to-float.ll
- copied, changed from r179820, llvm/trunk/test/CodeGen/R600/i8_to_double_to_float.ll
llvm/trunk/test/CodeGen/R600/jump-address.ll
- copied, changed from r179820, llvm/trunk/test/CodeGen/R600/jump_address.ll
llvm/trunk/test/CodeGen/R600/load.ll
llvm/trunk/test/CodeGen/R600/loop-address.ll
- copied, changed from r179820, llvm/trunk/test/CodeGen/R600/loop-adress.ll
llvm/trunk/test/CodeGen/R600/selectcc-cnd.ll
- copied, changed from r179820, llvm/trunk/test/CodeGen/R600/selectcc_cnde.ll
llvm/trunk/test/CodeGen/R600/selectcc-cnde-int.ll
- copied, changed from r179820, llvm/trunk/test/CodeGen/R600/selectcc_cnde_int.ll
llvm/trunk/test/CodeGen/R600/setcc.ll
- copied, changed from r179820, llvm/trunk/test/CodeGen/R600/setcc.v4i32.ll
llvm/trunk/test/CodeGen/R600/sint_to_fp.ll
llvm/trunk/test/CodeGen/R600/store.r600.ll
llvm/trunk/test/CodeGen/R600/udiv.ll
- copied, changed from r179820, llvm/trunk/test/CodeGen/R600/udiv.v4i32.ll
llvm/trunk/test/CodeGen/R600/uint_to_fp.ll
llvm/trunk/test/CodeGen/R600/urem.ll
- copied, changed from r179820, llvm/trunk/test/CodeGen/R600/urem.v4i32.ll
Removed:
llvm/trunk/test/CodeGen/R600/add.v4i32.ll
llvm/trunk/test/CodeGen/R600/and.v4i32.ll
llvm/trunk/test/CodeGen/R600/fadd.v4f32.ll
llvm/trunk/test/CodeGen/R600/fdiv.v4f32.ll
llvm/trunk/test/CodeGen/R600/fsub.v4f32.ll
llvm/trunk/test/CodeGen/R600/i8_to_double_to_float.ll
llvm/trunk/test/CodeGen/R600/jump_address.ll
llvm/trunk/test/CodeGen/R600/load.constant_addrspace.f32.ll
llvm/trunk/test/CodeGen/R600/load.i8.ll
llvm/trunk/test/CodeGen/R600/loop-adress.ll
llvm/trunk/test/CodeGen/R600/selectcc_cnde.ll
llvm/trunk/test/CodeGen/R600/selectcc_cnde_int.ll
llvm/trunk/test/CodeGen/R600/setcc.v4i32.ll
llvm/trunk/test/CodeGen/R600/store.v4f32.ll
llvm/trunk/test/CodeGen/R600/store.v4i32.ll
llvm/trunk/test/CodeGen/R600/udiv.v4i32.ll
llvm/trunk/test/CodeGen/R600/urem.v4i32.ll
llvm/trunk/test/CodeGen/R600/vec4-expand.ll
Modified:
llvm/trunk/test/CodeGen/R600/fadd.ll
llvm/trunk/test/CodeGen/R600/fmul.ll
llvm/trunk/test/CodeGen/R600/fsub.ll
llvm/trunk/test/CodeGen/R600/store.ll
Added: llvm/trunk/test/CodeGen/R600/README
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/README?rev=179828&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/README (added)
+++ llvm/trunk/test/CodeGen/R600/README Thu Apr 18 21:10:53 2013
@@ -0,0 +1,21 @@
++==============================================================================+
+| How to organize the lit tests |
++==============================================================================+
+
+- If you write a test for matching a single DAG opcode or intrinsic, it should
+ go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)
+
+- If you write a test that matches several DAG opcodes and checks for a single
+ ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
+ bfi_int.ll
+
+- For all other tests, use your best judgement for organizing tests and naming
+ the files.
+
++==============================================================================+
+| Naming conventions |
++==============================================================================+
+
+- Use dash '-' and not underscore '_' to separate words in file names, unless
+ the file is named after a DAG opcode or ISA instruction that has an
+ underscore '_' in its name.
Copied: llvm/trunk/test/CodeGen/R600/add.ll (from r179820, llvm/trunk/test/CodeGen/R600/add.v4i32.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/add.ll?p2=llvm/trunk/test/CodeGen/R600/add.ll&p1=llvm/trunk/test/CodeGen/R600/add.v4i32.ll&r1=179820&r2=179828&rev=179828&view=diff
==============================================================================
(empty)
Removed: llvm/trunk/test/CodeGen/R600/add.v4i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/add.v4i32.ll?rev=179827&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/add.v4i32.ll (original)
+++ llvm/trunk/test/CodeGen/R600/add.v4i32.ll (removed)
@@ -1,15 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
- %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
- %a = load <4 x i32> addrspace(1) * %in
- %b = load <4 x i32> addrspace(1) * %b_ptr
- %result = add <4 x i32> %a, %b
- store <4 x i32> %result, <4 x i32> addrspace(1)* %out
- ret void
-}
Copied: llvm/trunk/test/CodeGen/R600/and.ll (from r179820, llvm/trunk/test/CodeGen/R600/and.v4i32.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/and.ll?p2=llvm/trunk/test/CodeGen/R600/and.ll&p1=llvm/trunk/test/CodeGen/R600/and.v4i32.ll&r1=179820&r2=179828&rev=179828&view=diff
==============================================================================
(empty)
Removed: llvm/trunk/test/CodeGen/R600/and.v4i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/and.v4i32.ll?rev=179827&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/and.v4i32.ll (original)
+++ llvm/trunk/test/CodeGen/R600/and.v4i32.ll (removed)
@@ -1,15 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
- %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
- %a = load <4 x i32> addrspace(1) * %in
- %b = load <4 x i32> addrspace(1) * %b_ptr
- %result = and <4 x i32> %a, %b
- store <4 x i32> %result, <4 x i32> addrspace(1)* %out
- ret void
-}
Modified: llvm/trunk/test/CodeGen/R600/fadd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fadd.ll?rev=179828&r1=179827&r2=179828&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fadd.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fadd.ll Thu Apr 18 21:10:53 2013
@@ -1,8 +1,9 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; CHECK: @fadd_f32
; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-define void @test() {
+define void @fadd_f32() {
%r0 = call float @llvm.R600.load.input(i32 0)
%r1 = call float @llvm.R600.load.input(i32 1)
%r2 = fadd float %r0, %r1
@@ -14,3 +15,17 @@ declare float @llvm.R600.load.input(i32)
declare void @llvm.AMDGPU.store.output(float, i32)
+; CHECK: @fadd_v4f32
+; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+define void @fadd_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
+ %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
+ %a = load <4 x float> addrspace(1) * %in
+ %b = load <4 x float> addrspace(1) * %b_ptr
+ %result = fadd <4 x float> %a, %b
+ store <4 x float> %result, <4 x float> addrspace(1)* %out
+ ret void
+}
Removed: llvm/trunk/test/CodeGen/R600/fadd.v4f32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fadd.v4f32.ll?rev=179827&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fadd.v4f32.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fadd.v4f32.ll (removed)
@@ -1,15 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
- %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
- %a = load <4 x float> addrspace(1) * %in
- %b = load <4 x float> addrspace(1) * %b_ptr
- %result = fadd <4 x float> %a, %b
- store <4 x float> %result, <4 x float> addrspace(1)* %out
- ret void
-}
Copied: llvm/trunk/test/CodeGen/R600/fdiv.ll (from r179820, llvm/trunk/test/CodeGen/R600/fdiv.v4f32.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fdiv.ll?p2=llvm/trunk/test/CodeGen/R600/fdiv.ll&p1=llvm/trunk/test/CodeGen/R600/fdiv.v4f32.ll&r1=179820&r2=179828&rev=179828&view=diff
==============================================================================
(empty)
Removed: llvm/trunk/test/CodeGen/R600/fdiv.v4f32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fdiv.v4f32.ll?rev=179827&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fdiv.v4f32.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fdiv.v4f32.ll (removed)
@@ -1,19 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
- %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
- %a = load <4 x float> addrspace(1) * %in
- %b = load <4 x float> addrspace(1) * %b_ptr
- %result = fdiv <4 x float> %a, %b
- store <4 x float> %result, <4 x float> addrspace(1)* %out
- ret void
-}
Modified: llvm/trunk/test/CodeGen/R600/fmul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fmul.ll?rev=179828&r1=179827&r2=179828&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fmul.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fmul.ll Thu Apr 18 21:10:53 2013
@@ -1,8 +1,9 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; CHECK: @fmul_f32
; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-define void @test() {
+define void @fmul_f32() {
%r0 = call float @llvm.R600.load.input(i32 0)
%r1 = call float @llvm.R600.load.input(i32 1)
%r2 = fmul float %r0, %r1
@@ -14,3 +15,17 @@ declare float @llvm.R600.load.input(i32)
declare void @llvm.AMDGPU.store.output(float, i32)
+; CHECK: @fmul_v4f32
+; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+define void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
+ %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
+ %a = load <4 x float> addrspace(1) * %in
+ %b = load <4 x float> addrspace(1) * %b_ptr
+ %result = fmul <4 x float> %a, %b
+ store <4 x float> %result, <4 x float> addrspace(1)* %out
+ ret void
+}
Added: llvm/trunk/test/CodeGen/R600/fp_to_sint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fp_to_sint.ll?rev=179828&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fp_to_sint.ll (added)
+++ llvm/trunk/test/CodeGen/R600/fp_to_sint.ll Thu Apr 18 21:10:53 2013
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+
+; CHECK: @fp_to_sint_v4i32
+; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+define void @fp_to_sint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
+ %value = load <4 x float> addrspace(1) * %in
+ %result = fptosi <4 x float> %value to <4 x i32>
+ store <4 x i32> %result, <4 x i32> addrspace(1)* %out
+ ret void
+}
Added: llvm/trunk/test/CodeGen/R600/fp_to_uint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fp_to_uint.ll?rev=179828&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fp_to_uint.ll (added)
+++ llvm/trunk/test/CodeGen/R600/fp_to_uint.ll Thu Apr 18 21:10:53 2013
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+
+; CHECK: @fp_to_uint_v4i32
+; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+define void @fp_to_uint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
+ %value = load <4 x float> addrspace(1) * %in
+ %result = fptoui <4 x float> %value to <4 x i32>
+ store <4 x i32> %result, <4 x i32> addrspace(1)* %out
+ ret void
+}
Modified: llvm/trunk/test/CodeGen/R600/fsub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fsub.ll?rev=179828&r1=179827&r2=179828&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fsub.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fsub.ll Thu Apr 18 21:10:53 2013
@@ -1,8 +1,9 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; CHECK: @fsub_f32
; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
-define void @test() {
+define void @fsub_f32() {
%r0 = call float @llvm.R600.load.input(i32 0)
%r1 = call float @llvm.R600.load.input(i32 1)
%r2 = fsub float %r0, %r1
@@ -14,3 +15,17 @@ declare float @llvm.R600.load.input(i32)
declare void @llvm.AMDGPU.store.output(float, i32)
+; CHECK: @fsub_v4f32
+; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+define void @fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
+ %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
+ %a = load <4 x float> addrspace(1) * %in
+ %b = load <4 x float> addrspace(1) * %b_ptr
+ %result = fsub <4 x float> %a, %b
+ store <4 x float> %result, <4 x float> addrspace(1)* %out
+ ret void
+}
Removed: llvm/trunk/test/CodeGen/R600/fsub.v4f32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/fsub.v4f32.ll?rev=179827&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/fsub.v4f32.ll (original)
+++ llvm/trunk/test/CodeGen/R600/fsub.v4f32.ll (removed)
@@ -1,15 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
- %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
- %a = load <4 x float> addrspace(1) * %in
- %b = load <4 x float> addrspace(1) * %b_ptr
- %result = fsub <4 x float> %a, %b
- store <4 x float> %result, <4 x float> addrspace(1)* %out
- ret void
-}
Copied: llvm/trunk/test/CodeGen/R600/i8-to-double-to-float.ll (from r179820, llvm/trunk/test/CodeGen/R600/i8_to_double_to_float.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/i8-to-double-to-float.ll?p2=llvm/trunk/test/CodeGen/R600/i8-to-double-to-float.ll&p1=llvm/trunk/test/CodeGen/R600/i8_to_double_to_float.ll&r1=179820&r2=179828&rev=179828&view=diff
==============================================================================
(empty)
Removed: llvm/trunk/test/CodeGen/R600/i8_to_double_to_float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/i8_to_double_to_float.ll?rev=179827&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/i8_to_double_to_float.ll (original)
+++ llvm/trunk/test/CodeGen/R600/i8_to_double_to_float.ll (removed)
@@ -1,11 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-define void @test(float addrspace(1)* %out, i8 addrspace(1)* %in) {
- %1 = load i8 addrspace(1)* %in
- %2 = uitofp i8 %1 to double
- %3 = fptrunc double %2 to float
- store float %3, float addrspace(1)* %out
- ret void
-}
Copied: llvm/trunk/test/CodeGen/R600/jump-address.ll (from r179820, llvm/trunk/test/CodeGen/R600/jump_address.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/jump-address.ll?p2=llvm/trunk/test/CodeGen/R600/jump-address.ll&p1=llvm/trunk/test/CodeGen/R600/jump_address.ll&r1=179820&r2=179828&rev=179828&view=diff
==============================================================================
(empty)
Removed: llvm/trunk/test/CodeGen/R600/jump_address.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/jump_address.ll?rev=179827&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/jump_address.ll (original)
+++ llvm/trunk/test/CodeGen/R600/jump_address.ll (removed)
@@ -1,52 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-; CHECK: JUMP @3
-; CHECK: EXPORT
-; CHECK-NOT: EXPORT
-
-define void @main() #0 {
-main_body:
- %0 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %1 = extractelement <4 x float> %0, i32 0
- %2 = bitcast float %1 to i32
- %3 = icmp eq i32 %2, 0
- %4 = sext i1 %3 to i32
- %5 = bitcast i32 %4 to float
- %6 = bitcast float %5 to i32
- %7 = icmp ne i32 %6, 0
- br i1 %7, label %ENDIF, label %ELSE
-
-ELSE: ; preds = %main_body
- %8 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
- %9 = extractelement <4 x float> %8, i32 0
- %10 = bitcast float %9 to i32
- %11 = icmp eq i32 %10, 1
- %12 = sext i1 %11 to i32
- %13 = bitcast i32 %12 to float
- %14 = bitcast float %13 to i32
- %15 = icmp ne i32 %14, 0
- br i1 %15, label %IF13, label %ENDIF
-
-ENDIF: ; preds = %IF13, %ELSE, %main_body
- %temp.0 = phi float [ 0xFFF8000000000000, %main_body ], [ 0.000000e+00, %ELSE ], [ 0.000000e+00, %IF13 ]
- %temp1.0 = phi float [ 0.000000e+00, %main_body ], [ %23, %IF13 ], [ 0.000000e+00, %ELSE ]
- %temp2.0 = phi float [ 1.000000e+00, %main_body ], [ 0.000000e+00, %ELSE ], [ 0.000000e+00, %IF13 ]
- %temp3.0 = phi float [ 5.000000e-01, %main_body ], [ 0.000000e+00, %ELSE ], [ 0.000000e+00, %IF13 ]
- %16 = insertelement <4 x float> undef, float %temp.0, i32 0
- %17 = insertelement <4 x float> %16, float %temp1.0, i32 1
- %18 = insertelement <4 x float> %17, float %temp2.0, i32 2
- %19 = insertelement <4 x float> %18, float %temp3.0, i32 3
- call void @llvm.R600.store.swizzle(<4 x float> %19, i32 0, i32 0)
- ret void
-
-IF13: ; preds = %ELSE
- %20 = load <4 x float> addrspace(8)* null
- %21 = extractelement <4 x float> %20, i32 0
- %22 = fsub float -0.000000e+00, %21
- %23 = fadd float 0xFFF8000000000000, %22
- br label %ENDIF
-}
-
-declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
-
-attributes #0 = { "ShaderType"="0" }
Removed: llvm/trunk/test/CodeGen/R600/load.constant_addrspace.f32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/load.constant_addrspace.f32.ll?rev=179827&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/load.constant_addrspace.f32.ll (original)
+++ llvm/trunk/test/CodeGen/R600/load.constant_addrspace.f32.ll (removed)
@@ -1,9 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;CHECK: VTX_READ_32 T{{[0-9]+\.X, T[0-9]+\.X}}
-
-define void @test(float addrspace(1)* %out, float addrspace(2)* %in) {
- %1 = load float addrspace(2)* %in
- store float %1, float addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/load.i8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/load.i8.ll?rev=179827&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/load.i8.ll (original)
+++ llvm/trunk/test/CodeGen/R600/load.i8.ll (removed)
@@ -1,10 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
-
-define void @test(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
- %1 = load i8 addrspace(1)* %in
- %2 = zext i8 %1 to i32
- store i32 %2, i32 addrspace(1)* %out
- ret void
-}
Added: llvm/trunk/test/CodeGen/R600/load.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/load.ll?rev=179828&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/load.ll (added)
+++ llvm/trunk/test/CodeGen/R600/load.ll Thu Apr 18 21:10:53 2013
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+
+; Load an i8 value from the global address space.
+; CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
+
+define void @load_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
+ %1 = load i8 addrspace(1)* %in
+ %2 = zext i8 %1 to i32
+ store i32 %2, i32 addrspace(1)* %out
+ ret void
+}
+
+; Load a f32 value from the constant address space.
+; CHECK: VTX_READ_32 T{{[0-9]+\.X, T[0-9]+\.X}}
+
+define void @load_const_addrspace_f32(float addrspace(1)* %out, float addrspace(2)* %in) {
+ %1 = load float addrspace(2)* %in
+ store float %1, float addrspace(1)* %out
+ ret void
+}
Copied: llvm/trunk/test/CodeGen/R600/loop-address.ll (from r179820, llvm/trunk/test/CodeGen/R600/loop-adress.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/loop-address.ll?p2=llvm/trunk/test/CodeGen/R600/loop-address.ll&p1=llvm/trunk/test/CodeGen/R600/loop-adress.ll&r1=179820&r2=179828&rev=179828&view=diff
==============================================================================
(empty)
Removed: llvm/trunk/test/CodeGen/R600/loop-adress.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/loop-adress.ll?rev=179827&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/loop-adress.ll (original)
+++ llvm/trunk/test/CodeGen/R600/loop-adress.ll (removed)
@@ -1,44 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;CHECK: TEX
-;CHECK: ALU_PUSH
-;CHECK: JUMP @4
-;CHECK: ELSE @16
-;CHECK: TEX
-;CHECK: LOOP_START_DX10 @15
-;CHECK: LOOP_BREAK @14
-;CHECK: POP @16
-
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-n32:64"
-target triple = "r600--"
-
-define void @loop_ge(i32 addrspace(1)* nocapture %out, i32 %iterations) #0 {
-entry:
- %cmp5 = icmp sgt i32 %iterations, 0
- br i1 %cmp5, label %for.body, label %for.end
-
-for.body: ; preds = %for.body, %entry
- %i.07.in = phi i32 [ %i.07, %for.body ], [ %iterations, %entry ]
- %ai.06 = phi i32 [ %add, %for.body ], [ 0, %entry ]
- %i.07 = add nsw i32 %i.07.in, -1
- %arrayidx = getelementptr inbounds i32 addrspace(1)* %out, i32 %ai.06
- store i32 %i.07, i32 addrspace(1)* %arrayidx, align 4, !tbaa !4
- %add = add nsw i32 %ai.06, 1
- %exitcond = icmp eq i32 %add, %iterations
- br i1 %exitcond, label %for.end, label %for.body
-
-for.end: ; preds = %for.body, %entry
- ret void
-}
-
-attributes #0 = { nounwind "fp-contract-model"="standard" "relocation-model"="pic" "ssp-buffers-size"="8" }
-
-!opencl.kernels = !{!0, !1, !2, !3}
-
-!0 = metadata !{void (i32 addrspace(1)*, i32)* @loop_ge}
-!1 = metadata !{null}
-!2 = metadata !{null}
-!3 = metadata !{null}
-!4 = metadata !{metadata !"int", metadata !5}
-!5 = metadata !{metadata !"omnipotent char", metadata !6}
-!6 = metadata !{metadata !"Simple C/C++ TBAA"}
Copied: llvm/trunk/test/CodeGen/R600/selectcc-cnd.ll (from r179820, llvm/trunk/test/CodeGen/R600/selectcc_cnde.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/selectcc-cnd.ll?p2=llvm/trunk/test/CodeGen/R600/selectcc-cnd.ll&p1=llvm/trunk/test/CodeGen/R600/selectcc_cnde.ll&r1=179820&r2=179828&rev=179828&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/R600/selectcc-cnde-int.ll (from r179820, llvm/trunk/test/CodeGen/R600/selectcc_cnde_int.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/selectcc-cnde-int.ll?p2=llvm/trunk/test/CodeGen/R600/selectcc-cnde-int.ll&p1=llvm/trunk/test/CodeGen/R600/selectcc_cnde_int.ll&r1=179820&r2=179828&rev=179828&view=diff
==============================================================================
(empty)
Removed: llvm/trunk/test/CodeGen/R600/selectcc_cnde.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/selectcc_cnde.ll?rev=179827&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/selectcc_cnde.ll (original)
+++ llvm/trunk/test/CodeGen/R600/selectcc_cnde.ll (removed)
@@ -1,11 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;CHECK-NOT: SETE
-;CHECK: CNDE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], 1.0, literal.x, [-0-9]+\(2.0}}
-define void @test(float addrspace(1)* %out, float addrspace(1)* %in) {
- %1 = load float addrspace(1)* %in
- %2 = fcmp oeq float %1, 0.0
- %3 = select i1 %2, float 1.0, float 2.0
- store float %3, float addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/selectcc_cnde_int.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/selectcc_cnde_int.ll?rev=179827&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/selectcc_cnde_int.ll (original)
+++ llvm/trunk/test/CodeGen/R600/selectcc_cnde_int.ll (removed)
@@ -1,11 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;CHECK-NOT: SETE_INT
-;CHECK: CNDE_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], 1, literal.x, 2}}
-define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
- %1 = load i32 addrspace(1)* %in
- %2 = icmp eq i32 %1, 0
- %3 = select i1 %2, i32 1, i32 2
- store i32 %3, i32 addrspace(1)* %out
- ret void
-}
Copied: llvm/trunk/test/CodeGen/R600/setcc.ll (from r179820, llvm/trunk/test/CodeGen/R600/setcc.v4i32.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/setcc.ll?p2=llvm/trunk/test/CodeGen/R600/setcc.ll&p1=llvm/trunk/test/CodeGen/R600/setcc.v4i32.ll&r1=179820&r2=179828&rev=179828&view=diff
==============================================================================
(empty)
Removed: llvm/trunk/test/CodeGen/R600/setcc.v4i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/setcc.v4i32.ll?rev=179827&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/setcc.v4i32.ll (original)
+++ llvm/trunk/test/CodeGen/R600/setcc.v4i32.ll (removed)
@@ -1,12 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-;CHECK: SETE_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
- %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
- %a = load <4 x i32> addrspace(1) * %in
- %b = load <4 x i32> addrspace(1) * %b_ptr
- %result = icmp eq <4 x i32> %a, %b
- %sext = sext <4 x i1> %result to <4 x i32>
- store <4 x i32> %sext, <4 x i32> addrspace(1)* %out
- ret void
-}
Added: llvm/trunk/test/CodeGen/R600/sint_to_fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/sint_to_fp.ll?rev=179828&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/sint_to_fp.ll (added)
+++ llvm/trunk/test/CodeGen/R600/sint_to_fp.ll Thu Apr 18 21:10:53 2013
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+
+; CHECK: @sint_to_fp_v4i32
+; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+define void @sint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+ %value = load <4 x i32> addrspace(1) * %in
+ %result = sitofp <4 x i32> %value to <4 x float>
+ store <4 x float> %result, <4 x float> addrspace(1)* %out
+ ret void
+}
Modified: llvm/trunk/test/CodeGen/R600/store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/store.ll?rev=179828&r1=179827&r2=179828&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/store.ll (original)
+++ llvm/trunk/test/CodeGen/R600/store.ll Thu Apr 18 21:10:53 2013
@@ -1,11 +1,13 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
-; CHECK: @store_float
+; floating-point store
+; EG-CHECK: @store_f32
; EG-CHECK: RAT_WRITE_CACHELESS_32_eg T{{[0-9]+\.X, T[0-9]+\.X}}, 1
+; SI-CHECK: @store_f32
; SI-CHECK: BUFFER_STORE_DWORD
-define void @store_float(float addrspace(1)* %out, float %in) {
+define void @store_f32(float addrspace(1)* %out, float %in) {
store float %in, float addrspace(1)* %out
ret void
}
Added: llvm/trunk/test/CodeGen/R600/store.r600.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/store.r600.ll?rev=179828&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/store.r600.ll (added)
+++ llvm/trunk/test/CodeGen/R600/store.r600.ll Thu Apr 18 21:10:53 2013
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+
+; XXX: Merge this test into store.ll once it is supported on SI
+
+; v4i32 store
+; EG-CHECK: @store_v4i32
+; EG-CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1
+
+define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+ %1 = load <4 x i32> addrspace(1) * %in
+ store <4 x i32> %1, <4 x i32> addrspace(1)* %out
+ ret void
+}
+
+; v4f32 store
+; EG-CHECK: @store_v4f32
+; EG-CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1
+define void @store_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
+ %1 = load <4 x float> addrspace(1) * %in
+ store <4 x float> %1, <4 x float> addrspace(1)* %out
+ ret void
+}
Removed: llvm/trunk/test/CodeGen/R600/store.v4f32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/store.v4f32.ll?rev=179827&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/store.v4f32.ll (original)
+++ llvm/trunk/test/CodeGen/R600/store.v4f32.ll (removed)
@@ -1,9 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1
-
-define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
- %1 = load <4 x float> addrspace(1) * %in
- store <4 x float> %1, <4 x float> addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/store.v4i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/store.v4i32.ll?rev=179827&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/store.v4i32.ll (original)
+++ llvm/trunk/test/CodeGen/R600/store.v4i32.ll (removed)
@@ -1,9 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1
-
-define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
- %1 = load <4 x i32> addrspace(1) * %in
- store <4 x i32> %1, <4 x i32> addrspace(1)* %out
- ret void
-}
Copied: llvm/trunk/test/CodeGen/R600/udiv.ll (from r179820, llvm/trunk/test/CodeGen/R600/udiv.v4i32.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/udiv.ll?p2=llvm/trunk/test/CodeGen/R600/udiv.ll&p1=llvm/trunk/test/CodeGen/R600/udiv.v4i32.ll&r1=179820&r2=179828&rev=179828&view=diff
==============================================================================
(empty)
Removed: llvm/trunk/test/CodeGen/R600/udiv.v4i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/udiv.v4i32.ll?rev=179827&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/udiv.v4i32.ll (original)
+++ llvm/trunk/test/CodeGen/R600/udiv.v4i32.ll (removed)
@@ -1,15 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;The code generated by udiv is long and complex and may frequently change.
-;The goal of this test is to make sure the ISel doesn't fail when it gets
-;a v4i32 udiv
-;CHECK: RETURN
-
-define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
- %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
- %a = load <4 x i32> addrspace(1) * %in
- %b = load <4 x i32> addrspace(1) * %b_ptr
- %result = udiv <4 x i32> %a, %b
- store <4 x i32> %result, <4 x i32> addrspace(1)* %out
- ret void
-}
Added: llvm/trunk/test/CodeGen/R600/uint_to_fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/uint_to_fp.ll?rev=179828&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/uint_to_fp.ll (added)
+++ llvm/trunk/test/CodeGen/R600/uint_to_fp.ll Thu Apr 18 21:10:53 2013
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+
+; CHECK: @uint_to_fp_v4i32
+; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+define void @uint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+ %value = load <4 x i32> addrspace(1) * %in
+ %result = uitofp <4 x i32> %value to <4 x float>
+ store <4 x float> %result, <4 x float> addrspace(1)* %out
+ ret void
+}
Copied: llvm/trunk/test/CodeGen/R600/urem.ll (from r179820, llvm/trunk/test/CodeGen/R600/urem.v4i32.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/urem.ll?p2=llvm/trunk/test/CodeGen/R600/urem.ll&p1=llvm/trunk/test/CodeGen/R600/urem.v4i32.ll&r1=179820&r2=179828&rev=179828&view=diff
==============================================================================
(empty)
Removed: llvm/trunk/test/CodeGen/R600/urem.v4i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/urem.v4i32.ll?rev=179827&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/urem.v4i32.ll (original)
+++ llvm/trunk/test/CodeGen/R600/urem.v4i32.ll (removed)
@@ -1,15 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;The code generated by urem is long and complex and may frequently change.
-;The goal of this test is to make sure the ISel doesn't fail when it gets
-;a v4i32 urem
-;CHECK: RETURN
-
-define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
- %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
- %a = load <4 x i32> addrspace(1) * %in
- %b = load <4 x i32> addrspace(1) * %b_ptr
- %result = urem <4 x i32> %a, %b
- store <4 x i32> %result, <4 x i32> addrspace(1)* %out
- ret void
-}
Removed: llvm/trunk/test/CodeGen/R600/vec4-expand.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/vec4-expand.ll?rev=179827&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/vec4-expand.ll (original)
+++ llvm/trunk/test/CodeGen/R600/vec4-expand.ll (removed)
@@ -1,53 +0,0 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-; CHECK: @fp_to_sint
-; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-define void @fp_to_sint(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
- %value = load <4 x float> addrspace(1) * %in
- %result = fptosi <4 x float> %value to <4 x i32>
- store <4 x i32> %result, <4 x i32> addrspace(1)* %out
- ret void
-}
-
-; CHECK: @fp_to_uint
-; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-define void @fp_to_uint(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
- %value = load <4 x float> addrspace(1) * %in
- %result = fptoui <4 x float> %value to <4 x i32>
- store <4 x i32> %result, <4 x i32> addrspace(1)* %out
- ret void
-}
-
-; CHECK: @sint_to_fp
-; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-define void @sint_to_fp(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
- %value = load <4 x i32> addrspace(1) * %in
- %result = sitofp <4 x i32> %value to <4 x float>
- store <4 x float> %result, <4 x float> addrspace(1)* %out
- ret void
-}
-
-; CHECK: @uint_to_fp
-; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-define void @uint_to_fp(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
- %value = load <4 x i32> addrspace(1) * %in
- %result = uitofp <4 x i32> %value to <4 x float>
- store <4 x float> %result, <4 x float> addrspace(1)* %out
- ret void
-}
More information about the llvm-commits
mailing list