[llvm] r179567 - Mips assembler: Explicit floating point condition register recognition.

[Jack Carter]

Author: jacksprat
Date: Mon Apr 15 17:21:55 2013
New Revision: 179567

URL: http://llvm.org/viewvc/llvm-project?rev=179567&view=rev
Log:
Mips assembler: Explicit floating point condition register recognition.

This patch allows the assembler to recognize $fcc0 
as a valid register for conditional move instructions. 

Corresponding test cases have been added.

Contributer: Vladimir Medic


Modified:
    llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
    llvm/trunk/test/MC/Mips/mips-fpu-instructions.s

Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=179567&r1=179566&r2=179567&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Mon Apr 15 17:21:55 2013
@@ -778,6 +778,9 @@ int MipsAsmParser::matchCPURegisterName(
 }
 int MipsAsmParser::matchRegisterName(StringRef Name, bool is64BitReg) {
 
+  if (Name.equals("fcc0"))
+    return Mips::FCC0;
+
   int CC;
   CC = matchCPURegisterName(Name);
   if (CC != -1)

Modified: llvm/trunk/test/MC/Mips/mips-fpu-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips-fpu-instructions.s?rev=179567&r1=179566&r2=179567&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips-fpu-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/mips-fpu-instructions.s Mon Apr 15 17:21:55 2013
@@ -156,6 +156,8 @@
 # CHECK:  mtc0    $9, $8, 3               # encoding: [0x03,0x40,0x89,0x40]
 # CHECK:  mfc2    $5, $7, 4               # encoding: [0x04,0x38,0x05,0x48]
 # CHECK:  mtc2    $9, $4, 5               # encoding: [0x05,0x20,0x89,0x48]
+# CHECK:  movf    $2, $1, $fcc0           # encoding: [0x01,0x10,0x20,0x00]
+# CHECK:  movt    $2, $1, $fcc0           # encoding: [0x01,0x10,0x21,0x00]
 
    cfc1    $a2,$0
    mfc1    $a2,$f7
@@ -175,3 +177,5 @@
    mtc0    $9, $8, 3
    mfc2    $5, $7, 4
    mtc2    $9, $4, 5
+   movf    $2, $1, $fcc0
+   movt    $2, $1, $fcc0