[PATCH] Inserting directives directly after inline asm blocks

Jack Carter Jack.Carter at imgtec.com
Fri Apr 12 16:00:58 PDT 2013


I am going to pull this patch request. We may have to mimic GCC in the end due to historical customer code expectations.

Thanks,

Jack
________________________________________
From: Jack Carter
Sent: Wednesday, April 10, 2013 7:16 AM
To: Eric Christopher
Cc: llvm-commits at cs.uiuc.edu
Subject: RE: [PATCH] Inserting directives directly after inline asm blocks

I have attached the small test case, along with the backend generated assembler and a dump of the assembled object files.

 **
This is my llvm compile:
/clang ../testcase_2.c -o testcase_2_gas.ll -emit-llvm -O3 -S -target mipsel-unknown-linux -std=gnu89
llc testcase_2_gas.ll -o testcase_2_gas.s -mcpu=mips32r2 -march=mipsel
mips-linux-gnu-gcc -c -mips32r2 -EL -fPIC -o testcase_2_gas.o testcase_2_gas.s
mips-linux-gnu-gcc -mips32r2 -O3 -EL -fPIC -o testcase_2_gas.exe testcase_2_gas.o

/mips/tools/mips/swpkgs/bin/run-on-qemu -3 -p -EL testcase_2_gas.exe
qemu: uncaught target signal 11 (Segmentation fault) - core dumped
/mips/tools/mips/swpkgs/bin/run-on-qemu: line 128: 13085 Segmentation fault      (core dump

**
This is my gcc compile:
mips-linux-gnu-gcc -mips32r2 -O3 -EL -fPIC -o testcase_2.exe ../testcase_2.c

/mips/tools/mips/swpkgs/bin/run-on-qemu -3 -p -EL testcase_2.exe
4
5

 **

In the disassembly the  final "JR" instruction has a NOP inserted between it and the next instruction for the llvm generated sequence whereas the gcc variant correctly doesn't. Both were produced by gas, but the gcc variant had the JR wrapped in .set noreorder/reorder pairs.

Jack
________________________________________
From: Eric Christopher [echristo at gmail.com]
Sent: Tuesday, April 09, 2013 9:20 PM
To: Jack Carter
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [PATCH] Inserting directives directly after inline asm blocks

Can you provide a full testcase and the output that gcc gives that you expect?

-eric

On Tue, Apr 9, 2013 at 8:57 PM, Jack Carter <Jack.Carter at imgtec.com> wrote:
> This would be all Mips targets. It has to do with supporting existing user inline assembler.
>
> Jack
> ________________________________________
> From: Eric Christopher [echristo at gmail.com]
> Sent: Tuesday, April 09, 2013 4:38 PM
> To: Jack Carter
> Cc: llvm-commits at cs.uiuc.edu
> Subject: Re: [PATCH] Inserting directives directly after inline asm blocks
>
> Eh? Which mips target is it doing this for?
>
> -eric
>
> On Tue, Apr 9, 2013 at 4:09 PM, Jack Carter <Jack.Carter at imgtec.com> wrote:
>> I would like to insert a Mips specific directive directly after every inline
>> asm block. I have done this by exposing AsmPrinter::EmitInlineAsm() and
>> making a Mips derivation that calls the parent and then inserts the
>> directive. I'm open to other ideas, but this seemed to be the most straight
>> forward.
>>
>> May I check it in?
>>
>> Background:
>>
>> The Mips assembler has been around before the compiler could handle things
>> like delay slot filling. So, the assembler would move instructions around to
>> create and fill the delayslot. The general sequence would look like this:
>>
>> .set reorder
>> add inst
>> load inst
>> branch and link inst <-- this instruction has a delay slot
>> store inst <-- this instruction is suppose to execute after the branch and
>> line returns
>> load inst
>> .set noreorder
>>
>> This would get transformed by the assembler as:
>>
>> add inst
>> branch and link inst <-- this instruction has a delay slot
>> load inst  <-- the load now goes into the delay slot and is executed before
>> the branch
>> store inst
>> load inst
>>
>> With modern compilers this isn't needed, but we are still saddled with the
>> directive .set reorder which is the default state historically. I have
>> encountered user code that looks like this:
>>
>>     // The first word. Notice, no 'D'
>>     {asm (
>>     ".set noreorder"
>>     "lw    %0,%1;"
>>     ".set reorder"
>>     : "=r" (i)
>>     : "m" (*(b+4))
>>     );}
>>
>> The .set reorder  messes with our compiler generated jumps and branches.
>>
>> GCC gets around this by wrapping each and every branch and jump with .set
>> noreorder/reorder pairs. A bit over the top.
>>
>> Thanks,
>>
>> Jack
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
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>>
>





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