[PATCH] Add peephole optimization to use LEA instructions of Intel Atom

[Nadav Rotem]

Hi Preston, 

Why are you doing this optimization after register allocation, or even during instruction selection ?  If LEAs are better, why not use them all the time ?  Why are you going through the convertToThreeAddress, and not just do the conversion ?  Other users of convertToThreeAddress won't benefit from it because it is guarded by the isAfterRA flag, and you don't really need any of the logic in convertToThreeAddress ?

Thanks,
Nadav

On Apr 11, 2013, at 3:09 PM, Preston Gurd <preston.gurd at intel.com> wrote:

> Hi nadav, sdt,
> 
> This patch adds a pass which runs after register allocation when an Intel Atom processor is the target. The LEA instruction in the current Atom processor is specifically optimized to work best when its result is to be used as part of a memory address. This patch finds load or store instructions which use a base and/or an index register. It looks for an instruction in the current basic block which sets the base and/or index in the previous 5 instructions and then attempts to convert the instruction into an LEA, using the existing convertToThreeAddress code. For instance, it could convert an add or a move into an LEA. Since the result of an LEA is available earlier than the result of an ADD or a Move, there can be less delay in starting the load or store which references the register.
> 
> This is done after register allocation. The convertToThreeAddress function needed to have slightly different behaviour when invoked after register allocation. It was then useful to convert move instructions to LEAs. Also, some instructions defined to take immediate operands can only be converted to LEAs after register allocation if the immediate operand is an absolute number.
> 
> This patch adds a lit test which verifies that the replacement of an ADD by and LEA is NOT done if it is not needed.
> 
> Please review. 
> 
> 
> http://llvm-reviews.chandlerc.com/D660
> 
> Files:
>  test/CodeGen/X86/atom-fixup-lea2.ll
>  test/CodeGen/X86/lsr-static-addr.ll
>  test/CodeGen/X86/atom-fixup-lea1.ll
>  test/CodeGen/X86/atom-fixup-lea3.ll
>  lib/Target/X86/X86.td
>  lib/Target/X86/X86Subtarget.cpp
>  lib/Target/X86/X86TargetMachine.cpp
>  lib/Target/X86/X86InstrInfo.cpp
>  lib/Target/X86/X86Subtarget.h
>  lib/Target/X86/X86InstrInfo.h
>  lib/Target/X86/X86.h
>  lib/Target/X86/X86FixupLEAs.cpp
>  lib/Target/X86/CMakeLists.txt
> <D660.1.patch>_______________________________________________
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