[llvm] r179171 - ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.
Tim Northover
Tim.Northover at arm.com
Wed Apr 10 05:08:36 PDT 2013
Author: tnorthover
Date: Wed Apr 10 07:08:35 2013
New Revision: 179171
URL: http://llvm.org/viewvc/llvm-project?rev=179171&view=rev
Log:
ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.
These instructions aren't universally available, but depend on a specific
extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new
feature is appropriate.
This also enables the feature by default on A-class cores which usually have
these extensions, to avoid breaking existing code and act as a sensible
default.
Added:
llvm/trunk/test/MC/ARM/arm-thumb-trustzone.s (with props)
llvm/trunk/test/MC/ARM/arm-trustzone.s (with props)
llvm/trunk/test/MC/Disassembler/ARM/arm-thumb-trustzone.txt (with props)
llvm/trunk/test/MC/Disassembler/ARM/arm-trustzone.txt (with props)
Modified:
llvm/trunk/lib/Target/ARM/ARM.td
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
llvm/trunk/lib/Target/ARM/ARMSubtarget.h
llvm/trunk/test/MC/ARM/basic-arm-instructions.s
llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt
Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=179171&r1=179170&r2=179171&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Wed Apr 10 07:08:35 2013
@@ -59,6 +59,8 @@ def FeatureSlowFPBrcc : SubtargetFeature
"FP compare + branch is slow">;
def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
"Floating point unit supports single precision only">;
+def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
+ "Enable support for TrustZone security extensions">;
// Some processors have FP multiply-accumulate instructions that don't
// play nicely with other VFP / NEON instructions, and it's generally better
@@ -144,29 +146,33 @@ include "ARMSchedule.td"
def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
"Cortex-A5 ARM processors",
[FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
- FeatureVMLxForwarding, FeatureT2XtPk]>;
+ FeatureVMLxForwarding, FeatureT2XtPk,
+ FeatureTrustZone]>;
def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
"Cortex-A8 ARM processors",
[FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
- FeatureVMLxForwarding, FeatureT2XtPk]>;
+ FeatureVMLxForwarding, FeatureT2XtPk,
+ FeatureTrustZone]>;
def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
"Cortex-A9 ARM processors",
[FeatureVMLxForwarding,
FeatureT2XtPk, FeatureFP16,
- FeatureAvoidPartialCPSR]>;
+ FeatureAvoidPartialCPSR,
+ FeatureTrustZone]>;
def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
"Swift ARM processors",
[FeatureNEONForFP, FeatureT2XtPk,
FeatureVFP4, FeatureMP, FeatureHWDiv,
FeatureHWDivARM, FeatureAvoidPartialCPSR,
FeatureAvoidMOVsShOp,
- FeatureHasSlowFPVMLx]>;
+ FeatureHasSlowFPVMLx, FeatureTrustZone]>;
// FIXME: It has not been determined if A15 has these features.
def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
"Cortex-A15 ARM processors",
[FeatureT2XtPk, FeatureFP16,
- FeatureAvoidPartialCPSR]>;
+ FeatureAvoidPartialCPSR,
+ FeatureTrustZone]>;
def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
"Cortex-R5 ARM processors",
[FeatureSlowFPBrcc, FeatureHWDivARM,
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=179171&r1=179170&r2=179171&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Apr 10 07:08:35 2013
@@ -221,6 +221,9 @@ def HasDB : Predicate<"Subtar
def HasMP : Predicate<"Subtarget->hasMPExtension()">,
AssemblerPredicate<"FeatureMP",
"mp-extensions">;
+def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
+ AssemblerPredicate<"FeatureTrustZone",
+ "TrustZone">;
def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
def IsThumb : Predicate<"Subtarget->isThumb()">,
@@ -2077,7 +2080,7 @@ let isCall = 1, isTerminator = 1, isRetu
// Secure Monitor Call is a system instruction.
def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
- []> {
+ []>, Requires<[IsARM, HasTrustZone]> {
bits<4> opt;
let Inst{23-4} = 0b01100000000000000111;
let Inst{3-0} = opt;
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=179171&r1=179170&r2=179171&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Apr 10 07:08:35 2013
@@ -3449,7 +3449,8 @@ def t2DBG : T2I<(outs), (ins imm0_15:$op
// Secure Monitor Call is a system instruction.
// Option = Inst{19-16}
-def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", []> {
+def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
+ []>, Requires<[IsThumb2, HasTrustZone]> {
let Inst{31-27} = 0b11110;
let Inst{26-20} = 0b1111111;
let Inst{15-12} = 0b1000;
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=179171&r1=179170&r2=179171&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Wed Apr 10 07:08:35 2013
@@ -91,6 +91,7 @@ void ARMSubtarget::initializeEnvironment
HasRAS = false;
HasMPExtension = false;
FPOnlySP = false;
+ HasTrustZone = false;
AllowsUnalignedMem = false;
Thumb2DSP = false;
UseNaClTrap = false;
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=179171&r1=179170&r2=179171&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Wed Apr 10 07:08:35 2013
@@ -148,6 +148,9 @@ protected:
/// precision.
bool FPOnlySP;
+ /// HasTrustZone - if true, processor supports TrustZone security extensions
+ bool HasTrustZone;
+
/// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
/// accesses for some types. For details, see
/// ARMTargetLowering::allowsUnalignedMemoryAccesses().
@@ -251,6 +254,7 @@ public:
bool hasVMLxForwarding() const { return HasVMLxForwarding; }
bool isFPBrccSlow() const { return SlowFPBrcc; }
bool isFPOnlySP() const { return FPOnlySP; }
+ bool hasTrustZone() const { return HasTrustZone; }
bool prefers32BitThumb() const { return Pref32BitThumb; }
bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
Added: llvm/trunk/test/MC/ARM/arm-thumb-trustzone.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm-thumb-trustzone.s?rev=179171&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/arm-thumb-trustzone.s (added)
+++ llvm/trunk/test/MC/ARM/arm-thumb-trustzone.s Wed Apr 10 07:08:35 2013
@@ -0,0 +1,25 @@
+@ RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ
+@ RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ
+
+ .syntax unified
+ .globl _func
+
+@ Check that the assembler processes SMC instructions when TrustZone support is
+@ active and that it rejects them when this feature is not enabled
+
+_func:
+@ CHECK: _func
+
+
+ at ------------------------------------------------------------------------------
+@ SMC
+ at ------------------------------------------------------------------------------
+ smc #0xf
+ ite eq
+ smceq #0
+
+@ NOTZ-NOT: smc #15
+@ NOTZ-NOT: smceq #0
+@ TZ: smc #15 @ encoding: [0xff,0xf7,0x00,0x80]
+@ TZ: ite eq @ encoding: [0x0c,0xbf]
+@ TZ: smceq #0 @ encoding: [0xf0,0xf7,0x00,0x80]
Propchange: llvm/trunk/test/MC/ARM/arm-thumb-trustzone.s
------------------------------------------------------------------------------
svn:eol-style = native
Added: llvm/trunk/test/MC/ARM/arm-trustzone.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm-trustzone.s?rev=179171&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/arm-trustzone.s (added)
+++ llvm/trunk/test/MC/ARM/arm-trustzone.s Wed Apr 10 07:08:35 2013
@@ -0,0 +1,24 @@
+@ RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ
+@ RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ
+
+ .syntax unified
+ .globl _func
+
+@ Check that the assembler processes SMC instructions when TrustZone support is
+@ active and that it rejects them when this feature is not enabled
+
+_func:
+@ CHECK: _func
+
+
+ at ------------------------------------------------------------------------------
+@ SMC
+ at ------------------------------------------------------------------------------
+ smc #0xf
+ smceq #0
+
+@ NOTZ-NOT: smc #15
+@ NOTZ-NOT: smceq #0
+@ TZ: smc #15 @ encoding: [0x7f,0x00,0x60,0xe1]
+@ TZ: smceq #0 @ encoding: [0x70,0x00,0x60,0x01]
+
Propchange: llvm/trunk/test/MC/ARM/arm-trustzone.s
------------------------------------------------------------------------------
svn:eol-style = native
Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=179171&r1=179170&r2=179171&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Apr 10 07:08:35 2013
@@ -1791,15 +1791,6 @@ Lforward:
@ CHECK: shsub8gt r4, r8, r2 @ encoding: [0xf2,0x4f,0x38,0xc6]
@------------------------------------------------------------------------------
-@ SMC
- at ------------------------------------------------------------------------------
- smc #0xf
- smceq #0
-
-@ CHECK: smc #15 @ encoding: [0x7f,0x00,0x60,0xe1]
-@ CHECK: smceq #0 @ encoding: [0x70,0x00,0x60,0x01]
-
- at ------------------------------------------------------------------------------
@ SMLABB/SMLABT/SMLATB/SMLATT
@------------------------------------------------------------------------------
smlabb r3, r1, r9, r0
Added: llvm/trunk/test/MC/Disassembler/ARM/arm-thumb-trustzone.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-thumb-trustzone.txt?rev=179171&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/arm-thumb-trustzone.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/arm-thumb-trustzone.txt Wed Apr 10 07:08:35 2013
@@ -0,0 +1,17 @@
+# RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ
+# RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ
+
+
+#------------------------------------------------------------------------------
+# SMC
+#------------------------------------------------------------------------------
+
+0xff 0xf7 0x00 0x80
+0x0c 0xbf
+0xf0 0xf7 0x00 0x80
+
+# NOTZ-NOT: smc #15
+# NOTZ-NOT: smceq #0
+# TZ: smc #15
+# TZ: ite eq
+# TZ: smceq #0
Propchange: llvm/trunk/test/MC/Disassembler/ARM/arm-thumb-trustzone.txt
------------------------------------------------------------------------------
svn:eol-style = native
Added: llvm/trunk/test/MC/Disassembler/ARM/arm-trustzone.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-trustzone.txt?rev=179171&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/arm-trustzone.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/arm-trustzone.txt Wed Apr 10 07:08:35 2013
@@ -0,0 +1,16 @@
+# RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ
+# RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ
+
+
+#------------------------------------------------------------------------------
+# SMC
+#------------------------------------------------------------------------------
+
+0x7f 0x00 0x60 0xe1
+0x70 0x00 0x60 0x01
+
+# NOTZ-NOT: smc #15
+# NOTZ-NOT: smceq #0
+# TZ: smc #15
+# TZ: smceq #0
+
Propchange: llvm/trunk/test/MC/Disassembler/ARM/arm-trustzone.txt
------------------------------------------------------------------------------
svn:eol-style = native
Modified: llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt?rev=179171&r1=179170&r2=179171&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt Wed Apr 10 07:08:35 2013
@@ -1442,15 +1442,6 @@
0xf2 0x4f 0x38 0xc6
#------------------------------------------------------------------------------
-# SMC
-#------------------------------------------------------------------------------
-# CHECK: smc #15
-# CHECK: smceq #0
-
-0x7f 0x00 0x60 0xe1
-0x70 0x00 0x60 0x01
-
-#------------------------------------------------------------------------------
# SMLABB/SMLABT/SMLATB/SMLATT
#------------------------------------------------------------------------------
# CHECK: smlabb r3, r1, r9, r0
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