[llvm] r178821 - MachineScheduler: format DEBUG output.
Andrew Trick
atrick at apple.com
Thu Apr 4 17:31:29 PDT 2013
Author: atrick
Date: Thu Apr 4 19:31:29 2013
New Revision: 178821
URL: http://llvm.org/viewvc/llvm-project?rev=178821&view=rev
Log:
MachineScheduler: format DEBUG output.
I'm getting more serious about tuning and enabling on x86/ARM. Start
by making the trace readable.
Modified:
llvm/trunk/lib/CodeGen/MachineScheduler.cpp
Modified: llvm/trunk/lib/CodeGen/MachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=178821&r1=178820&r2=178821&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Thu Apr 4 19:31:29 2013
@@ -305,7 +305,7 @@ void MachineScheduler::print(raw_ostream
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
void ReadyQueue::dump() {
- dbgs() << Name << ": ";
+ dbgs() << " " << Name << ": ";
for (unsigned i = 0, e = Queue.size(); i < e; ++i)
dbgs() << Queue[i]->NodeNum << " ";
dbgs() << "\n";
@@ -1192,7 +1192,7 @@ protected:
SchedCandidate &Candidate);
#ifndef NDEBUG
- void traceCandidate(const SchedCandidate &Cand, const SchedBoundary &Zone);
+ void traceCandidate(const SchedCandidate &Cand);
#endif
};
} // namespace
@@ -1403,8 +1403,8 @@ void ConvergingScheduler::SchedBoundary:
CheckPending = true;
IsResourceLimited = getCriticalCount() > std::max(ExpectedLatency, CurrCycle);
- DEBUG(dbgs() << " *** " << Available.getName() << " cycle "
- << CurrCycle << '\n');
+ DEBUG(dbgs() << " " << Available.getName()
+ << " Cycle: " << CurrCycle << '\n');
}
/// Add the given processor resource to this scheduled zone.
@@ -1870,9 +1870,7 @@ const char *ConvergingScheduler::getReas
llvm_unreachable("Unknown reason!");
}
-void ConvergingScheduler::traceCandidate(const SchedCandidate &Cand,
- const SchedBoundary &Zone) {
- const char *Label = getReasonStr(Cand.Reason);
+void ConvergingScheduler::traceCandidate(const SchedCandidate &Cand) {
PressureElement P;
unsigned ResIdx = 0;
unsigned Latency = 0;
@@ -1907,21 +1905,21 @@ void ConvergingScheduler::traceCandidate
Latency = Cand.SU->getDepth();
break;
}
- dbgs() << Label << " " << Zone.Available.getName() << " ";
+ dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason);
if (P.isValid())
- dbgs() << TRI->getRegPressureSetName(P.PSetID) << ":" << P.UnitIncrease
- << " ";
+ dbgs() << " " << TRI->getRegPressureSetName(P.PSetID)
+ << ":" << P.UnitIncrease << " ";
else
- dbgs() << " ";
+ dbgs() << " ";
if (ResIdx)
- dbgs() << SchedModel->getProcResource(ResIdx)->Name << " ";
+ dbgs() << " " << SchedModel->getProcResource(ResIdx)->Name << " ";
else
- dbgs() << " ";
+ dbgs() << " ";
if (Latency)
- dbgs() << Latency << " cycles ";
+ dbgs() << " " << Latency << " cycles ";
else
- dbgs() << " ";
- Cand.SU->dump(DAG);
+ dbgs() << " ";
+ dbgs() << '\n';
}
#endif
@@ -1950,14 +1948,14 @@ void ConvergingScheduler::pickNodeFromQu
if (TryCand.ResDelta == SchedResourceDelta())
TryCand.initResourceDelta(DAG, SchedModel);
Cand.setBest(TryCand);
- DEBUG(traceCandidate(Cand, Zone));
+ DEBUG(traceCandidate(Cand));
}
}
}
static void tracePick(const ConvergingScheduler::SchedCandidate &Cand,
bool IsTop) {
- DEBUG(dbgs() << "Pick " << (IsTop ? "top" : "bot")
+ DEBUG(dbgs() << "Pick " << (IsTop ? "Top" : "Bot")
<< " SU(" << Cand.SU->NodeNum << ") "
<< ConvergingScheduler::getReasonStr(Cand.Reason) << '\n');
}
@@ -2069,10 +2067,7 @@ SUnit *ConvergingScheduler::pickNode(boo
if (SU->isBottomReady())
Bot.removeReady(SU);
- DEBUG(dbgs() << "*** " << (IsTopNode ? "Top" : "Bottom")
- << " Scheduling Instruction in cycle "
- << (IsTopNode ? Top.CurrCycle : Bot.CurrCycle) << '\n';
- SU->dump(DAG));
+ DEBUG(dbgs() << "Scheduling " << *SU->getInstr());
return SU;
}
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