[PATCH] More direct types in PowerPC AltiVec instructions

[Ulrich Weigand]

Hi Bill,

in you commit message for r178277 you wrote:

>I have not been able to do anything for the
>following classes of instructions:

>(1) Vector logicals.  These don't have corresponding intrinsics and
>don't have a single obvious vector type.  So far as I can tell I need
>to leave these as VRRC.  Affected instructions are:  VAND, VANDC,
>VNOR, VOR, VXOR, V_SET0.

>(2) Instructions that make use of vector shuffle.  The selection code
>promotes all shuffles to v16i8, so any pattern that matches on a
>shuffle is constrained.  I haven't found any way to make the patterns
>match on their natural types, so I plan to leave these as VRRC.
>Affected instructions are:  VMRG*, VSPLTB, VSPLTH, VSPLTW, VPKUHUM,
>VPKUWUM.

>From looking at the generated .inc files, it seems TableGen does
actually choose specific types to match.  In the cases listed
under (1), this is always v4i32, while in the cases listed
under (2), it is always v16i8.

Using the attached patch replaces the remaining uses of VRRC in
ISEL DAG patterns by those types; the generated .inc files are
completely identical (except for comments), and thus no change
in code generation is expected.

I think for clarity it would make sense to apply this patch;
after all, this is what will actually be matched ...

Thoughts?


B.t.w. if the patch is applied, the only remaining uses of
VRRC in a pattern are the bitconvert Pat pattern.  I was
unable to rewrite those to use types without getting
TableGen errors.

Bye,
Ulrich


(See attached file: diff-llvm-moredirecttypes)
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