R600/SI Patchset: Initial support for compute shaders
Tom Stellard
tom at stellard.net
Mon Apr 1 14:17:26 PDT 2013
Hi,
I've rebased these patches on top of the current master branch. Let me
know how they look.
Thanks,
Tom
On Wed, Mar 13, 2013 at 02:07:38PM -0700, Tom Stellard wrote:
> Hi,
>
> Here is version two of this patchset with the requested changes.
>
> -Tom
> From 25421dc77752c5ca547130e1b760980c0155efc5 Mon Sep 17 00:00:00 2001
> From: Tom Stellard <thomas.stellard at amd.com>
> Date: Wed, 6 Mar 2013 17:28:55 +0000
> Subject: [PATCH 1/6] R600/SI: Avoid generating S_MOVs with 64-bit immediates v2
>
> SITargetLowering::analyzeImmediate() was converting the 64-bit values
> to 32-bit and then checking if they were an inline immediate. Some
> of these conversions caused this check to succeed and produced
> S_MOV instructions with 64-bit immediates, which are illegal.
>
> v2:
> - Clean up logic
> ---
> lib/Target/R600/SIISelLowering.cpp | 7 +++++--
> test/CodeGen/R600/imm.ll | 26 ++++++++++++++++++++++++++
> 2 files changed, 31 insertions(+), 2 deletions(-)
> create mode 100644 test/CodeGen/R600/imm.ll
>
> diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
> index fead115..413be61 100644
> --- a/lib/Target/R600/SIISelLowering.cpp
> +++ b/lib/Target/R600/SIISelLowering.cpp
> @@ -426,9 +426,12 @@ int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
> float F;
> } Imm;
>
> - if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N))
> + if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
> + if (Node->getZExtValue() >> 32) {
> + return -1;
> + }
> Imm.I = Node->getSExtValue();
> - else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N))
> + } else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N))
> Imm.F = Node->getValueAPF().convertToFloat();
> else
> return -1; // It isn't an immediate
> diff --git a/test/CodeGen/R600/imm.ll b/test/CodeGen/R600/imm.ll
> new file mode 100644
> index 0000000..b43f917
> --- /dev/null
> +++ b/test/CodeGen/R600/imm.ll
> @@ -0,0 +1,26 @@
> +; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
> +
> +; XXX: Enable once SI supports buffer stores
> +; XFAIL: *
> +
> +; Use a 64-bit value with lo bits that can be represented as an inline constant
> +; CHECK: @i64_imm_inline_lo
> +; CHECK: S_MOV_B32 [[LO:SGPR[0-9]+]], 5
> +; CHECK: V_MOV_B32_e32 [[LO_VGPR:VGPR[0-9]+]], [[LO]]
> +; CHECK: BUFFER_STORE_DWORDX2 [[LO_VGPR]]_
> +define void @i64_imm_inline_lo(i64 addrspace(1) *%out) {
> +entry:
> + store i64 1311768464867721221, i64 addrspace(1) *%out ; 0x1234567800000005
> + ret void
> +}
> +
> +; Use a 64-bit value with hi bits that can be represented as an inline constant
> +; CHECK: @i64_imm_inline_hi
> +; CHECK: S_MOV_B32 [[HI:SGPR[0-9]+]], 5
> +; CHECK: V_MOV_B32_e32 [[HI_VGPR:VGPR[0-9]+]], [[HI]]
> +; CHECK: BUFFER_STORE_DWORDX2 {{VGPR[0-9]+}}_[[HI_VGPR]]
> +define void @i64_imm_inline_hi(i64 addrspace(1) *%out) {
> +entry:
> + store i64 21780256376, i64 addrspace(1) *%out ; 0x0000000512345678
> + ret void
> +}
> --
> 1.7.3.4
>
> From f9e3e69331f8a2e9b5d17d7ea5825e0a476ef7d5 Mon Sep 17 00:00:00 2001
> From: Tom Stellard <thomas.stellard at amd.com>
> Date: Fri, 8 Mar 2013 13:28:18 -0500
> Subject: [PATCH 2/6] R600/SI: Add processor types for each SI variant
>
> ---
> lib/Target/R600/AMDILDeviceInfo.cpp | 3 ++-
> lib/Target/R600/Processors.td | 6 ++++--
> test/CodeGen/R600/imm.ll | 2 +-
> test/CodeGen/R600/llvm.SI.fs.interp.constant.ll | 2 +-
> test/CodeGen/R600/llvm.SI.sample.ll | 2 +-
> 5 files changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/lib/Target/R600/AMDILDeviceInfo.cpp b/lib/Target/R600/AMDILDeviceInfo.cpp
> index 9605fbe..9cc2083 100644
> --- a/lib/Target/R600/AMDILDeviceInfo.cpp
> +++ b/lib/Target/R600/AMDILDeviceInfo.cpp
> @@ -79,7 +79,8 @@ AMDGPUDevice* getDeviceFromName(const std::string &deviceName,
> " on 32bit pointers!");
> #endif
> return new AMDGPUNIDevice(ptr);
> - } else if (deviceName == "SI") {
> + } else if (deviceName == "tahiti" || deviceName == "pitcairn" ||
> + deviceName == "verde" || deviceName == "oland") {
> return new AMDGPUSIDevice(ptr);
> } else {
> #if DEBUG
> diff --git a/lib/Target/R600/Processors.td b/lib/Target/R600/Processors.td
> index 868810c..86534f6 100644
> --- a/lib/Target/R600/Processors.td
> +++ b/lib/Target/R600/Processors.td
> @@ -26,5 +26,7 @@ def : Proc<"barts", R600_EG_Itin, [FeatureByteAddress, FeatureImages]>;
> def : Proc<"turks", R600_EG_Itin, [FeatureByteAddress, FeatureImages]>;
> def : Proc<"caicos", R600_EG_Itin, [FeatureByteAddress, FeatureImages]>;
> def : Proc<"cayman", R600_EG_Itin, [FeatureByteAddress, FeatureImages, FeatureFP64]>;
> -def : Proc<"SI", SI_Itin, [Feature64BitPtr]>;
> -
> +def : Proc<"tahiti", SI_Itin, [Feature64BitPtr, FeatureFP64]>;
> +def : Proc<"pitcairn", SI_Itin, [Feature64BitPtr, FeatureFP64]>;
> +def : Proc<"verde", SI_Itin, [Feature64BitPtr, FeatureFP64]>;
> +def : Proc<"oland", SI_Itin, [Feature64BitPtr, FeatureFP64]>;
> diff --git a/test/CodeGen/R600/imm.ll b/test/CodeGen/R600/imm.ll
> index b43f917..02b7309 100644
> --- a/test/CodeGen/R600/imm.ll
> +++ b/test/CodeGen/R600/imm.ll
> @@ -1,4 +1,4 @@
> -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
> +; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
>
> ; XXX: Enable once SI supports buffer stores
> ; XFAIL: *
> diff --git a/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll b/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll
> index 0c19f14..b715be9 100644
> --- a/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll
> +++ b/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll
> @@ -1,4 +1,4 @@
> -;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
> +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
>
> ;CHECK: S_MOV_B32
> ;CHECK-NEXT: V_INTERP_MOV_F32
> diff --git a/test/CodeGen/R600/llvm.SI.sample.ll b/test/CodeGen/R600/llvm.SI.sample.ll
> index d397f3b..be5a946 100644
> --- a/test/CodeGen/R600/llvm.SI.sample.ll
> +++ b/test/CodeGen/R600/llvm.SI.sample.ll
> @@ -1,4 +1,4 @@
> -;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
> +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
>
> ;CHECK: IMAGE_SAMPLE
> ;CHECK-NEXT: S_WAITCNT 1904
> --
> 1.7.3.4
>
> From 1ee5c51c8ea0f571e0ebedf6e33498151ec5f78c Mon Sep 17 00:00:00 2001
> From: Tom Stellard <thomas.stellard at amd.com>
> Date: Wed, 13 Mar 2013 16:04:34 -0400
> Subject: [PATCH 3/6] R600: Add RV670 processor
>
> This is an R600 GPU with double support.
> ---
> lib/Target/R600/Processors.td | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/lib/Target/R600/Processors.td b/lib/Target/R600/Processors.td
> index 86534f6..76ccb10 100644
> --- a/lib/Target/R600/Processors.td
> +++ b/lib/Target/R600/Processors.td
> @@ -15,6 +15,7 @@ class Proc<string Name, ProcessorItineraries itin, list<SubtargetFeature> Featur
> : Processor<Name, itin, Features>;
> def : Proc<"", R600_EG_Itin, [FeatureR600ALUInst]>;
> def : Proc<"r600", R600_EG_Itin, [FeatureR600ALUInst]>;
> +def : Proc<"rv670", R600_EG_Itin, [FeatureR600ALUInst, FeatureFP64]>;
> def : Proc<"rv710", R600_EG_Itin, []>;
> def : Proc<"rv730", R600_EG_Itin, []>;
> def : Proc<"rv770", R600_EG_Itin, [FeatureFP64]>;
> --
> 1.7.3.4
>
> From 6872fc7257e42527e706b055d08b60d523920fec Mon Sep 17 00:00:00 2001
> From: Tom Stellard <thomas.stellard at amd.com>
> Date: Wed, 24 Oct 2012 16:20:20 -0400
> Subject: [PATCH 4/6] R600/SI: Use same names for corresponding MUBUF operands and encoding fields
>
> The code emitter knows how to encode operands whose name matches one of
> the encoding fields. If there is no match, the code emitter relies on
> the order of the operand and field definitions to determine how operands
> should be encoding. Matching by order makes it easy to accidentally break
> the instruction encodings, so we prefer to match by name.
> ---
> lib/Target/R600/SIInstrFormats.td | 50 ++++++++++++++++++------------------
> lib/Target/R600/SIInstrInfo.td | 4 +-
> 2 files changed, 27 insertions(+), 27 deletions(-)
>
> diff --git a/lib/Target/R600/SIInstrFormats.td b/lib/Target/R600/SIInstrFormats.td
> index 3891ddb..f737ddd 100644
> --- a/lib/Target/R600/SIInstrFormats.td
> +++ b/lib/Target/R600/SIInstrFormats.td
> @@ -284,33 +284,33 @@ let Uses = [EXEC] in {
> class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
> Enc64<outs, ins, asm, pattern> {
>
> - bits<8> VDATA;
> - bits<12> OFFSET;
> - bits<1> OFFEN;
> - bits<1> IDXEN;
> - bits<1> GLC;
> - bits<1> ADDR64;
> - bits<1> LDS;
> - bits<8> VADDR;
> - bits<7> SRSRC;
> - bits<1> SLC;
> - bits<1> TFE;
> - bits<8> SOFFSET;
> -
> - let Inst{11-0} = OFFSET;
> - let Inst{12} = OFFEN;
> - let Inst{13} = IDXEN;
> - let Inst{14} = GLC;
> - let Inst{15} = ADDR64;
> - let Inst{16} = LDS;
> + bits<12> offset;
> + bits<1> offen;
> + bits<1> idxen;
> + bits<1> glc;
> + bits<1> addr64;
> + bits<1> lds;
> + bits<8> vaddr;
> + bits<8> vdata;
> + bits<7> srsrc;
> + bits<1> slc;
> + bits<1> tfe;
> + bits<8> soffset;
> +
> + let Inst{11-0} = offset;
> + let Inst{12} = offen;
> + let Inst{13} = idxen;
> + let Inst{14} = glc;
> + let Inst{15} = addr64;
> + let Inst{16} = lds;
> let Inst{24-18} = op;
> let Inst{31-26} = 0x38; //encoding
> - let Inst{39-32} = VADDR;
> - let Inst{47-40} = VDATA;
> - let Inst{52-48} = SRSRC{6-2};
> - let Inst{54} = SLC;
> - let Inst{55} = TFE;
> - let Inst{63-56} = SOFFSET;
> + let Inst{39-32} = vaddr;
> + let Inst{47-40} = vdata;
> + let Inst{52-48} = srsrc{6-2};
> + let Inst{54} = slc;
> + let Inst{55} = tfe;
> + let Inst{63-56} = soffset;
>
> let VM_CNT = 1;
> let EXP_CNT = 1;
> diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
> index 260c651..1b09ded 100644
> --- a/lib/Target/R600/SIInstrInfo.td
> +++ b/lib/Target/R600/SIInstrInfo.td
> @@ -276,11 +276,11 @@ class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBU
>
> class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
> op,
> - (outs regClass:$dst),
> + (outs regClass:$vdata),
> (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
> i1imm:$lds, VReg_32:$vaddr, SReg_128:$srsrc, i1imm:$slc,
> i1imm:$tfe, SSrc_32:$soffset),
> - asm#" $dst, $offset, $offen, $idxen, $glc, $addr64, "
> + asm#" $vdata, $offset, $offen, $idxen, $glc, $addr64, "
> #"$lds, $vaddr, $srsrc, $slc, $tfe, $soffset",
> []> {
> let mayLoad = 1;
> --
> 1.7.3.4
>
> From 88be02fa329d8527425f652962e40c5c3d4af3c1 Mon Sep 17 00:00:00 2001
> From: Tom Stellard <thomas.stellard at amd.com>
> Date: Thu, 25 Oct 2012 10:36:05 -0400
> Subject: [PATCH 5/6] R600/SI: Simplify MUBUF helper class for loads
>
> ---
> lib/Target/R600/SIInstrInfo.td | 23 ++++++++++++++++-------
> lib/Target/R600/SIInstructions.td | 17 +++++++----------
> 2 files changed, 23 insertions(+), 17 deletions(-)
>
> diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
> index 1b09ded..d0cd468 100644
> --- a/lib/Target/R600/SIInstrInfo.td
> +++ b/lib/Target/R600/SIInstrInfo.td
> @@ -274,17 +274,26 @@ class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBU
> let mayLoad = 0;
> }
>
> -class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
> +class MUBUF_Load_Helper <bits<7> op, string name, RegisterClass regClass,
> + list<dag> Pat> : MUBUF <
> op,
> (outs regClass:$vdata),
> - (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
> - i1imm:$lds, VReg_32:$vaddr, SReg_128:$srsrc, i1imm:$slc,
> - i1imm:$tfe, SSrc_32:$soffset),
> - asm#" $vdata, $offset, $offen, $idxen, $glc, $addr64, "
> - #"$lds, $vaddr, $srsrc, $slc, $tfe, $soffset",
> - []> {
> + (ins i16imm:$offset, SReg_128:$srsrc, VReg_32:$vaddr),
> + name#" $vdata, ($srsrc + $offset)[$vaddr]",
> + Pat> {
> +
> let mayLoad = 1;
> let mayStore = 0;
> +
> + // Encoding
> + let offen = 0;
> + let idxen = 1;
> + let glc = 0;
> + let addr64 = 0;
> + let lds = 0;
> + let slc = 0;
> + let tfe = 0;
> + let soffset = 128; // ZERO
> }
>
> class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
> diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
> index 0ab9e4e..44f35b9 100644
> --- a/lib/Target/R600/SIInstructions.td
> +++ b/lib/Target/R600/SIInstructions.td
> @@ -394,7 +394,13 @@ defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">;
> //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>;
> //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>;
> //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>;
> -def BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>;
> +
> +def BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <
> + 0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128,
> + [(set VReg_128:$vdata, (int_SI_vs_load_input SReg_128:$srsrc,
> + IMM12bit:$offset,
> + VReg_32:$vaddr))]>;
> +
> //def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>;
> //def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>;
> //def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>;
> @@ -1145,15 +1151,6 @@ def : Pat <
> (SI_KILL (V_MOV_B32_e32 0xbf800000))
> >;
>
> -/* int_SI_vs_load_input */
> -def : Pat<
> - (int_SI_vs_load_input SReg_128:$tlst, IMM12bit:$attr_offset,
> - VReg_32:$buf_idx_vgpr),
> - (BUFFER_LOAD_FORMAT_XYZW imm:$attr_offset, 0, 1, 0, 0, 0,
> - VReg_32:$buf_idx_vgpr, SReg_128:$tlst,
> - 0, 0, 0)
> ->;
> -
> /* int_SI_export */
> def : Pat <
> (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
> --
> 1.7.3.4
>
> From f2a9a591eaf840bd3fefb14e22a372ce2b7fd7bb Mon Sep 17 00:00:00 2001
> From: Tom Stellard <thomas.stellard at amd.com>
> Date: Mon, 4 Mar 2013 15:12:16 -0500
> Subject: [PATCH 6/6] R600/SI: Add support for buffer stores v2
>
> v2:
> - Use the ADDR64 bit
> ---
> lib/Target/R600/AMDGPUCallingConv.td | 8 +++++++-
> lib/Target/R600/AMDGPUISelLowering.h | 1 +
> lib/Target/R600/AMDILISelDAGToDAG.cpp | 23 +++++++++++++++++++++++
> lib/Target/R600/SIISelLowering.cpp | 31 +++++++++++++++++++++++++++++++
> lib/Target/R600/SIISelLowering.h | 1 +
> lib/Target/R600/SIInstrInfo.td | 26 ++++++++++++++++++++++++++
> lib/Target/R600/SIInstructions.td | 10 ++++++++--
> lib/Target/R600/SIRegisterInfo.td | 2 +-
> test/CodeGen/R600/imm.ll | 3 ---
> test/CodeGen/R600/store.ll | 11 +++++++++++
> 10 files changed, 109 insertions(+), 7 deletions(-)
> create mode 100644 test/CodeGen/R600/store.ll
>
> diff --git a/lib/Target/R600/AMDGPUCallingConv.td b/lib/Target/R600/AMDGPUCallingConv.td
> index 45ae37e..9c30515 100644
> --- a/lib/Target/R600/AMDGPUCallingConv.td
> +++ b/lib/Target/R600/AMDGPUCallingConv.td
> @@ -32,8 +32,14 @@ def CC_SI : CallingConv<[
> VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
> VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
> VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31
> - ]>>>
> + ]>>>,
>
> + // This is the default for i64 values.
> + // XXX: We should change this once clang understands the CC_AMDGPU.
> + CCIfType<[i64], CCAssignToRegWithShadow<
> + [ SGPR0, SGPR2, SGPR4, SGPR6, SGPR8, SGPR10, SGPR12, SGPR14 ],
> + [ SGPR1, SGPR3, SGPR5, SGPR7, SGPR9, SGPR11, SGPR13, SGPR15 ]
> + >>
> ]>;
>
> def CC_AMDGPU : CallingConv<[
> diff --git a/lib/Target/R600/AMDGPUISelLowering.h b/lib/Target/R600/AMDGPUISelLowering.h
> index f31b646..c2a79ea 100644
> --- a/lib/Target/R600/AMDGPUISelLowering.h
> +++ b/lib/Target/R600/AMDGPUISelLowering.h
> @@ -116,6 +116,7 @@ enum {
> BRANCH_COND,
> // End AMDIL ISD Opcodes
> BITALIGN,
> + BUFFER_STORE,
> DWORDADDR,
> FRACT,
> FMAX,
> diff --git a/lib/Target/R600/AMDILISelDAGToDAG.cpp b/lib/Target/R600/AMDILISelDAGToDAG.cpp
> index e77b9dc..3e58881 100644
> --- a/lib/Target/R600/AMDILISelDAGToDAG.cpp
> +++ b/lib/Target/R600/AMDILISelDAGToDAG.cpp
> @@ -162,6 +162,29 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
> }
> switch (Opc) {
> default: break;
> + case ISD::BUILD_PAIR: {
> + SDValue RC, SubReg0, SubReg1;
> + const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
> + if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
> + break;
> + }
> + if (N->getValueType(0) == MVT::i128) {
> + RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32);
> + SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, MVT::i32);
> + SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32);
> + } else if (N->getValueType(0) == MVT::i64) {
> + RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32);
> + SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
> + SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
> + } else {
> + llvm_unreachable("Unhandled value type for BUILD_PAIR");
> + }
> + const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
> + N->getOperand(1), SubReg1 };
> + return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
> + N->getDebugLoc(), N->getValueType(0), Ops, 5);
> + }
> +
> case ISD::ConstantFP:
> case ISD::Constant: {
> const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
> diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
> index 413be61..7777f1f 100644
> --- a/lib/Target/R600/SIISelLowering.cpp
> +++ b/lib/Target/R600/SIISelLowering.cpp
> @@ -49,6 +49,7 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
>
> addRegisterClass(MVT::v4i32, &AMDGPU::VReg_128RegClass);
> addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
> + addRegisterClass(MVT::i128, &AMDGPU::SReg_128RegClass);
>
> addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
> addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
> @@ -68,6 +69,9 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
> setTargetDAGCombine(ISD::SELECT_CC);
>
> setTargetDAGCombine(ISD::SETCC);
> +
> + setOperationAction(ISD::STORE, MVT::i32, Custom);
> + setOperationAction(ISD::STORE, MVT::i64, Custom);
> }
>
> SDValue SITargetLowering::LowerFormalArguments(
> @@ -236,6 +240,7 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
> default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
> case ISD::BRCOND: return LowerBRCOND(Op, DAG);
> case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
> + case ISD::STORE: return LowerSTORE(Op, DAG);
> }
> return SDValue();
> }
> @@ -334,6 +339,32 @@ SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
> return Chain;
> }
>
> +#define RSRC_DATA_FORMAT 0xf00000000000
> +
> +SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
> + StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
> + SDValue Chain = Op.getOperand(0);
> + SDValue Value = Op.getOperand(1);
> + SDValue VirtualAddress = Op.getOperand(2);
> + DebugLoc DL = Op.getDebugLoc();
> +
> + if (StoreNode->getAddressSpace() != AMDGPUAS::GLOBAL_ADDRESS) {
> + return SDValue();
> + }
> +
> + SDValue SrcSrc = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i128,
> + DAG.getConstant(0, MVT::i64),
> + DAG.getConstant(RSRC_DATA_FORMAT, MVT::i64));
> +
> + SDValue Ops[2];
> + Ops[0] = DAG.getNode(AMDGPUISD::BUFFER_STORE, DL, MVT::Other, Chain,
> + Value, SrcSrc, VirtualAddress);
> + Ops[1] = Chain;
> +
> + return DAG.getMergeValues(Ops, 2, DL);
> +
> +}
> +
> SDValue SITargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
> SDValue LHS = Op.getOperand(0);
> SDValue RHS = Op.getOperand(1);
> diff --git a/lib/Target/R600/SIISelLowering.h b/lib/Target/R600/SIISelLowering.h
> index 0411565..ef0a8dc 100644
> --- a/lib/Target/R600/SIISelLowering.h
> +++ b/lib/Target/R600/SIISelLowering.h
> @@ -27,6 +27,7 @@ class SITargetLowering : public AMDGPUTargetLowering {
> void LowerSI_WQM(MachineInstr *MI, MachineBasicBlock &BB,
> MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
>
> + SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
> SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
> SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
>
> diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
> index d0cd468..8d5d8de 100644
> --- a/lib/Target/R600/SIInstrInfo.td
> +++ b/lib/Target/R600/SIInstrInfo.td
> @@ -26,6 +26,10 @@ def HI32 : SDNodeXForm<imm, [{
> return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
> }]>;
>
> +def SIbuffer_store : SDNode<"AMDGPUISD::BUFFER_STORE",
> + SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
> + [SDNPHasChain, SDNPMayStore]>;
> +
> def IMM8bitDWORD : ImmLeaf <
> i32, [{
> return (Imm & ~0x3FC) == 0;
> @@ -296,6 +300,28 @@ class MUBUF_Load_Helper <bits<7> op, string name, RegisterClass regClass,
> let soffset = 128; // ZERO
> }
>
> +class MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
> + ValueType VT> :
> + MUBUF <op, (outs), (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr),
> + name#" $vdata, $srsrc + $vaddr",
> + [(SIbuffer_store (VT vdataClass:$vdata), (i128 SReg_128:$srsrc),
> + (i64 VReg_64:$vaddr))]> {
> +
> + let mayLoad = 0;
> + let mayStore = 1;
> +
> + // Encoding
> + let offset = 0;
> + let offen = 0;
> + let idxen = 0;
> + let glc = 0;
> + let addr64 = 1;
> + let lds = 0;
> + let slc = 0;
> + let tfe = 0;
> + let soffset = 128; // ZERO
> +}
> +
> class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
> op,
> (outs regClass:$dst),
> diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
> index 44f35b9..a01e096 100644
> --- a/lib/Target/R600/SIInstructions.td
> +++ b/lib/Target/R600/SIInstructions.td
> @@ -414,8 +414,14 @@ def BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <
> //def BUFFER_LOAD_DWORDX4 : MUBUF_DWORDX4 <0x0000000e, "BUFFER_LOAD_DWORDX4", []>;
> //def BUFFER_STORE_BYTE : MUBUF_ <0x00000018, "BUFFER_STORE_BYTE", []>;
> //def BUFFER_STORE_SHORT : MUBUF_ <0x0000001a, "BUFFER_STORE_SHORT", []>;
> -//def BUFFER_STORE_DWORD : MUBUF_ <0x0000001c, "BUFFER_STORE_DWORD", []>;
> -//def BUFFER_STORE_DWORDX2 : MUBUF_DWORDX2 <0x0000001d, "BUFFER_STORE_DWORDX2", []>;
> +
> +def BUFFER_STORE_DWORD : MUBUF_Store_Helper <
> + 0x0000001c, "BUFFER_STORE_DWORD", VReg_32, i32
> +>;
> +
> +def BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper <
> + 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64, i64
> +>;
> //def BUFFER_STORE_DWORDX4 : MUBUF_DWORDX4 <0x0000001e, "BUFFER_STORE_DWORDX4", []>;
> //def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>;
> //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>;
> diff --git a/lib/Target/R600/SIRegisterInfo.td b/lib/Target/R600/SIRegisterInfo.td
> index 3dcad50..af74123 100644
> --- a/lib/Target/R600/SIRegisterInfo.td
> +++ b/lib/Target/R600/SIRegisterInfo.td
> @@ -151,7 +151,7 @@ def SReg_64 : RegisterClass<"AMDGPU", [i64, i1], 64,
> (add SGPR_64, VCCReg, EXECReg)
> >;
>
> -def SReg_128 : RegisterClass<"AMDGPU", [v16i8], 128, (add SGPR_128)>;
> +def SReg_128 : RegisterClass<"AMDGPU", [v16i8, i128], 128, (add SGPR_128)>;
>
> def SReg_256 : RegisterClass<"AMDGPU", [v32i8], 256, (add SGPR_256)>;
>
> diff --git a/test/CodeGen/R600/imm.ll b/test/CodeGen/R600/imm.ll
> index 02b7309..979efb0 100644
> --- a/test/CodeGen/R600/imm.ll
> +++ b/test/CodeGen/R600/imm.ll
> @@ -1,8 +1,5 @@
> ; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
>
> -; XXX: Enable once SI supports buffer stores
> -; XFAIL: *
> -
> ; Use a 64-bit value with lo bits that can be represented as an inline constant
> ; CHECK: @i64_imm_inline_lo
> ; CHECK: S_MOV_B32 [[LO:SGPR[0-9]+]], 5
> diff --git a/test/CodeGen/R600/store.ll b/test/CodeGen/R600/store.ll
> new file mode 100644
> index 0000000..4382bff
> --- /dev/null
> +++ b/test/CodeGen/R600/store.ll
> @@ -0,0 +1,11 @@
> +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
> +; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
> +
> +; CHECK: @store_float
> +; EG-CHECK: RAT_WRITE_CACHELESS_32_eg T{{[0-9]+\.X, T[0-9]+\.X}}, 1
> +; SI-CHECK: BUFFER_STORE_DWORD
> +
> +define void @store_float(float addrspace(1)* %out, float %in) {
> + store float %in, float addrspace(1)* %out
> + ret void
> +}
> --
> 1.7.3.4
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
-------------- next part --------------
>From 1fe83a34025b684afd09c3cb7fd7fe714883d5ef Mon Sep 17 00:00:00 2001
From: Tom Stellard <thomas.stellard at amd.com>
Date: Wed, 6 Mar 2013 17:28:55 +0000
Subject: [PATCH 1/6] R600/SI: Avoid generating S_MOVs with 64-bit immediates v2
SITargetLowering::analyzeImmediate() was converting the 64-bit values
to 32-bit and then checking if they were an inline immediate. Some
of these conversions caused this check to succeed and produced
S_MOV instructions with 64-bit immediates, which are illegal.
v2:
- Clean up logic
---
lib/Target/R600/SIISelLowering.cpp | 7 +++++--
test/CodeGen/R600/imm.ll | 26 ++++++++++++++++++++++++++
2 files changed, 31 insertions(+), 2 deletions(-)
create mode 100644 test/CodeGen/R600/imm.ll
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
index 6f0c307..7fa28d9 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -424,9 +424,12 @@ int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
float F;
} Imm;
- if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N))
+ if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
+ if (Node->getZExtValue() >> 32) {
+ return -1;
+ }
Imm.I = Node->getSExtValue();
- else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N))
+ } else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N))
Imm.F = Node->getValueAPF().convertToFloat();
else
return -1; // It isn't an immediate
diff --git a/test/CodeGen/R600/imm.ll b/test/CodeGen/R600/imm.ll
new file mode 100644
index 0000000..b43f917
--- /dev/null
+++ b/test/CodeGen/R600/imm.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
+
+; XXX: Enable once SI supports buffer stores
+; XFAIL: *
+
+; Use a 64-bit value with lo bits that can be represented as an inline constant
+; CHECK: @i64_imm_inline_lo
+; CHECK: S_MOV_B32 [[LO:SGPR[0-9]+]], 5
+; CHECK: V_MOV_B32_e32 [[LO_VGPR:VGPR[0-9]+]], [[LO]]
+; CHECK: BUFFER_STORE_DWORDX2 [[LO_VGPR]]_
+define void @i64_imm_inline_lo(i64 addrspace(1) *%out) {
+entry:
+ store i64 1311768464867721221, i64 addrspace(1) *%out ; 0x1234567800000005
+ ret void
+}
+
+; Use a 64-bit value with hi bits that can be represented as an inline constant
+; CHECK: @i64_imm_inline_hi
+; CHECK: S_MOV_B32 [[HI:SGPR[0-9]+]], 5
+; CHECK: V_MOV_B32_e32 [[HI_VGPR:VGPR[0-9]+]], [[HI]]
+; CHECK: BUFFER_STORE_DWORDX2 {{VGPR[0-9]+}}_[[HI_VGPR]]
+define void @i64_imm_inline_hi(i64 addrspace(1) *%out) {
+entry:
+ store i64 21780256376, i64 addrspace(1) *%out ; 0x0000000512345678
+ ret void
+}
--
1.7.3.4
-------------- next part --------------
>From a43eb4840439422fe8631712ed76751920976727 Mon Sep 17 00:00:00 2001
From: Tom Stellard <thomas.stellard at amd.com>
Date: Fri, 8 Mar 2013 13:28:18 -0500
Subject: [PATCH 2/6] R600/SI: Add processor types for each SI variant
---
lib/Target/R600/AMDILDeviceInfo.cpp | 3 ++-
lib/Target/R600/Processors.td | 6 ++++--
test/CodeGen/R600/imm.ll | 2 +-
test/CodeGen/R600/llvm.SI.fs.interp.constant.ll | 2 +-
test/CodeGen/R600/llvm.SI.sample.ll | 2 +-
test/CodeGen/R600/lshl.ll | 2 +-
test/CodeGen/R600/lshr.ll | 2 +-
test/CodeGen/R600/mulhu.ll | 2 +-
test/CodeGen/R600/seto.ll | 2 +-
test/CodeGen/R600/setuo.ll | 2 +-
10 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/lib/Target/R600/AMDILDeviceInfo.cpp b/lib/Target/R600/AMDILDeviceInfo.cpp
index 9605fbe..9cc2083 100644
--- a/lib/Target/R600/AMDILDeviceInfo.cpp
+++ b/lib/Target/R600/AMDILDeviceInfo.cpp
@@ -79,7 +79,8 @@ AMDGPUDevice* getDeviceFromName(const std::string &deviceName,
" on 32bit pointers!");
#endif
return new AMDGPUNIDevice(ptr);
- } else if (deviceName == "SI") {
+ } else if (deviceName == "tahiti" || deviceName == "pitcairn" ||
+ deviceName == "verde" || deviceName == "oland") {
return new AMDGPUSIDevice(ptr);
} else {
#if DEBUG
diff --git a/lib/Target/R600/Processors.td b/lib/Target/R600/Processors.td
index 868810c..86534f6 100644
--- a/lib/Target/R600/Processors.td
+++ b/lib/Target/R600/Processors.td
@@ -26,5 +26,7 @@ def : Proc<"barts", R600_EG_Itin, [FeatureByteAddress, FeatureImages]>;
def : Proc<"turks", R600_EG_Itin, [FeatureByteAddress, FeatureImages]>;
def : Proc<"caicos", R600_EG_Itin, [FeatureByteAddress, FeatureImages]>;
def : Proc<"cayman", R600_EG_Itin, [FeatureByteAddress, FeatureImages, FeatureFP64]>;
-def : Proc<"SI", SI_Itin, [Feature64BitPtr]>;
-
+def : Proc<"tahiti", SI_Itin, [Feature64BitPtr, FeatureFP64]>;
+def : Proc<"pitcairn", SI_Itin, [Feature64BitPtr, FeatureFP64]>;
+def : Proc<"verde", SI_Itin, [Feature64BitPtr, FeatureFP64]>;
+def : Proc<"oland", SI_Itin, [Feature64BitPtr, FeatureFP64]>;
diff --git a/test/CodeGen/R600/imm.ll b/test/CodeGen/R600/imm.ll
index b43f917..02b7309 100644
--- a/test/CodeGen/R600/imm.ll
+++ b/test/CodeGen/R600/imm.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
+; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
; XXX: Enable once SI supports buffer stores
; XFAIL: *
diff --git a/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll b/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll
index bf0cdaa..e45722c 100644
--- a/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll
+++ b/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll
@@ -1,4 +1,4 @@
-;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
;CHECK: S_MOV_B32
;CHECK-NEXT: V_INTERP_MOV_F32
diff --git a/test/CodeGen/R600/llvm.SI.sample.ll b/test/CodeGen/R600/llvm.SI.sample.ll
index c724395..5bdb246 100644
--- a/test/CodeGen/R600/llvm.SI.sample.ll
+++ b/test/CodeGen/R600/llvm.SI.sample.ll
@@ -1,4 +1,4 @@
-;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
;CHECK: IMAGE_SAMPLE
;CHECK: IMAGE_SAMPLE
diff --git a/test/CodeGen/R600/lshl.ll b/test/CodeGen/R600/lshl.ll
index 423adb9..fb698da 100644
--- a/test/CodeGen/R600/lshl.ll
+++ b/test/CodeGen/R600/lshl.ll
@@ -1,4 +1,4 @@
-;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
;CHECK: V_LSHLREV_B32_e32 VGPR0, 1, VGPR0
diff --git a/test/CodeGen/R600/lshr.ll b/test/CodeGen/R600/lshr.ll
index 551eac1..e0ed3ac 100644
--- a/test/CodeGen/R600/lshr.ll
+++ b/test/CodeGen/R600/lshr.ll
@@ -1,4 +1,4 @@
-;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
;CHECK: V_LSHRREV_B32_e32 VGPR0, 1, VGPR0
diff --git a/test/CodeGen/R600/mulhu.ll b/test/CodeGen/R600/mulhu.ll
index 28744e0..bc17a59 100644
--- a/test/CodeGen/R600/mulhu.ll
+++ b/test/CodeGen/R600/mulhu.ll
@@ -1,4 +1,4 @@
-;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
;CHECK: V_MOV_B32_e32 VGPR1, -1431655765
;CHECK-NEXT: V_MUL_HI_U32 VGPR0, VGPR0, VGPR1, 0, 0, 0, 0, 0
diff --git a/test/CodeGen/R600/seto.ll b/test/CodeGen/R600/seto.ll
index 5ab4b87..4622203 100644
--- a/test/CodeGen/R600/seto.ll
+++ b/test/CodeGen/R600/seto.ll
@@ -1,4 +1,4 @@
-;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
;CHECK: V_CMP_O_F32_e64 SGPR0_SGPR1, VGPR0, VGPR0, 0, 0, 0, 0
diff --git a/test/CodeGen/R600/setuo.ll b/test/CodeGen/R600/setuo.ll
index 3208355..0bf5801 100644
--- a/test/CodeGen/R600/setuo.ll
+++ b/test/CodeGen/R600/setuo.ll
@@ -1,4 +1,4 @@
-;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
;CHECK: V_CMP_U_F32_e64 SGPR0_SGPR1, VGPR0, VGPR0, 0, 0, 0, 0
--
1.7.3.4
-------------- next part --------------
>From ebde36463aab54e207a50b78c7b9c97e1f5021eb Mon Sep 17 00:00:00 2001
From: Tom Stellard <thomas.stellard at amd.com>
Date: Wed, 13 Mar 2013 16:04:34 -0400
Subject: [PATCH 3/6] R600: Add RV670 processor
This is an R600 GPU with double support.
---
lib/Target/R600/Processors.td | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/lib/Target/R600/Processors.td b/lib/Target/R600/Processors.td
index 86534f6..76ccb10 100644
--- a/lib/Target/R600/Processors.td
+++ b/lib/Target/R600/Processors.td
@@ -15,6 +15,7 @@ class Proc<string Name, ProcessorItineraries itin, list<SubtargetFeature> Featur
: Processor<Name, itin, Features>;
def : Proc<"", R600_EG_Itin, [FeatureR600ALUInst]>;
def : Proc<"r600", R600_EG_Itin, [FeatureR600ALUInst]>;
+def : Proc<"rv670", R600_EG_Itin, [FeatureR600ALUInst, FeatureFP64]>;
def : Proc<"rv710", R600_EG_Itin, []>;
def : Proc<"rv730", R600_EG_Itin, []>;
def : Proc<"rv770", R600_EG_Itin, [FeatureFP64]>;
--
1.7.3.4
-------------- next part --------------
>From be405789e3a61498e152e689e49d2699ec485c02 Mon Sep 17 00:00:00 2001
From: Tom Stellard <thomas.stellard at amd.com>
Date: Wed, 24 Oct 2012 16:20:20 -0400
Subject: [PATCH 4/6] R600/SI: Use same names for corresponding MUBUF operands and encoding fields
The code emitter knows how to encode operands whose name matches one of
the encoding fields. If there is no match, the code emitter relies on
the order of the operand and field definitions to determine how operands
should be encoding. Matching by order makes it easy to accidentally break
the instruction encodings, so we prefer to match by name.
---
lib/Target/R600/SIInstrFormats.td | 50 ++++++++++++++++++------------------
lib/Target/R600/SIInstrInfo.td | 4 +-
2 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/lib/Target/R600/SIInstrFormats.td b/lib/Target/R600/SIInstrFormats.td
index 3891ddb..f737ddd 100644
--- a/lib/Target/R600/SIInstrFormats.td
+++ b/lib/Target/R600/SIInstrFormats.td
@@ -284,33 +284,33 @@ let Uses = [EXEC] in {
class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
Enc64<outs, ins, asm, pattern> {
- bits<8> VDATA;
- bits<12> OFFSET;
- bits<1> OFFEN;
- bits<1> IDXEN;
- bits<1> GLC;
- bits<1> ADDR64;
- bits<1> LDS;
- bits<8> VADDR;
- bits<7> SRSRC;
- bits<1> SLC;
- bits<1> TFE;
- bits<8> SOFFSET;
-
- let Inst{11-0} = OFFSET;
- let Inst{12} = OFFEN;
- let Inst{13} = IDXEN;
- let Inst{14} = GLC;
- let Inst{15} = ADDR64;
- let Inst{16} = LDS;
+ bits<12> offset;
+ bits<1> offen;
+ bits<1> idxen;
+ bits<1> glc;
+ bits<1> addr64;
+ bits<1> lds;
+ bits<8> vaddr;
+ bits<8> vdata;
+ bits<7> srsrc;
+ bits<1> slc;
+ bits<1> tfe;
+ bits<8> soffset;
+
+ let Inst{11-0} = offset;
+ let Inst{12} = offen;
+ let Inst{13} = idxen;
+ let Inst{14} = glc;
+ let Inst{15} = addr64;
+ let Inst{16} = lds;
let Inst{24-18} = op;
let Inst{31-26} = 0x38; //encoding
- let Inst{39-32} = VADDR;
- let Inst{47-40} = VDATA;
- let Inst{52-48} = SRSRC{6-2};
- let Inst{54} = SLC;
- let Inst{55} = TFE;
- let Inst{63-56} = SOFFSET;
+ let Inst{39-32} = vaddr;
+ let Inst{47-40} = vdata;
+ let Inst{52-48} = srsrc{6-2};
+ let Inst{54} = slc;
+ let Inst{55} = tfe;
+ let Inst{63-56} = soffset;
let VM_CNT = 1;
let EXP_CNT = 1;
diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
index 617f0b8..e77a886 100644
--- a/lib/Target/R600/SIInstrInfo.td
+++ b/lib/Target/R600/SIInstrInfo.td
@@ -285,11 +285,11 @@ class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBU
class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
op,
- (outs regClass:$dst),
+ (outs regClass:$vdata),
(ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
i1imm:$lds, VReg_32:$vaddr, SReg_128:$srsrc, i1imm:$slc,
i1imm:$tfe, SSrc_32:$soffset),
- asm#" $dst, $offset, $offen, $idxen, $glc, $addr64, "
+ asm#" $vdata, $offset, $offen, $idxen, $glc, $addr64, "
#"$lds, $vaddr, $srsrc, $slc, $tfe, $soffset",
[]> {
let mayLoad = 1;
--
1.7.3.4
-------------- next part --------------
>From f0fecf3abe98757a01d52135ec1e9c898ee3bbaf Mon Sep 17 00:00:00 2001
From: Tom Stellard <thomas.stellard at amd.com>
Date: Thu, 25 Oct 2012 10:36:05 -0400
Subject: [PATCH 5/6] R600/SI: Simplify MUBUF helper class for loads
---
lib/Target/R600/SIInstrInfo.td | 23 ++++++++++++++++-------
lib/Target/R600/SIInstructions.td | 25 +++++++++++--------------
2 files changed, 27 insertions(+), 21 deletions(-)
diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
index e77a886..6df2797 100644
--- a/lib/Target/R600/SIInstrInfo.td
+++ b/lib/Target/R600/SIInstrInfo.td
@@ -283,17 +283,26 @@ class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBU
let mayLoad = 0;
}
-class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
+class MUBUF_Load_Helper <bits<7> op, string name, RegisterClass regClass,
+ list<dag> Pat> : MUBUF <
op,
(outs regClass:$vdata),
- (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
- i1imm:$lds, VReg_32:$vaddr, SReg_128:$srsrc, i1imm:$slc,
- i1imm:$tfe, SSrc_32:$soffset),
- asm#" $vdata, $offset, $offen, $idxen, $glc, $addr64, "
- #"$lds, $vaddr, $srsrc, $slc, $tfe, $soffset",
- []> {
+ (ins i16imm:$offset, SReg_128:$srsrc, VReg_32:$vaddr),
+ name#" $vdata, ($srsrc + $offset)[$vaddr]",
+ Pat> {
+
let mayLoad = 1;
let mayStore = 0;
+
+ // Encoding
+ let offen = 0;
+ let idxen = 1;
+ let glc = 0;
+ let addr64 = 0;
+ let lds = 0;
+ let slc = 0;
+ let tfe = 0;
+ let soffset = 128; // ZERO
}
class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
index 4f734f9..bbe035a 100644
--- a/lib/Target/R600/SIInstructions.td
+++ b/lib/Target/R600/SIInstructions.td
@@ -394,7 +394,13 @@ defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">;
//def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>;
//def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>;
//def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>;
-def BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>;
+
+def BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <
+ 0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128,
+ [(set VReg_128:$vdata, (int_SI_vs_load_input SReg_128:$srsrc,
+ IMM12bit:$offset,
+ VReg_32:$vaddr))]>;
+
//def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>;
//def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>;
//def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>;
@@ -403,9 +409,9 @@ def BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT
//def BUFFER_LOAD_SBYTE : MUBUF_ <0x00000009, "BUFFER_LOAD_SBYTE", []>;
//def BUFFER_LOAD_USHORT : MUBUF_ <0x0000000a, "BUFFER_LOAD_USHORT", []>;
//def BUFFER_LOAD_SSHORT : MUBUF_ <0x0000000b, "BUFFER_LOAD_SSHORT", []>;
-def BUFFER_LOAD_DWORD : MUBUF_Load_Helper <0x0000000c, "BUFFER_LOAD_DWORD", VReg_32>;
-def BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64>;
-def BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128>;
+def BUFFER_LOAD_DWORD : MUBUF_Load_Helper <0x0000000c, "BUFFER_LOAD_DWORD", VReg_32, []>;
+def BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64, []>;
+def BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128, []>;
//def BUFFER_STORE_BYTE : MUBUF_ <0x00000018, "BUFFER_STORE_BYTE", []>;
//def BUFFER_STORE_SHORT : MUBUF_ <0x0000001a, "BUFFER_STORE_SHORT", []>;
//def BUFFER_STORE_DWORD : MUBUF_ <0x0000001c, "BUFFER_STORE_DWORD", []>;
@@ -1193,15 +1199,6 @@ def : Pat <
(SI_KILL (V_MOV_B32_e32 0xbf800000))
>;
-/* int_SI_vs_load_input */
-def : Pat<
- (int_SI_vs_load_input SReg_128:$tlst, IMM12bit:$attr_offset,
- VReg_32:$buf_idx_vgpr),
- (BUFFER_LOAD_FORMAT_XYZW imm:$attr_offset, 0, 1, 0, 0, 0,
- VReg_32:$buf_idx_vgpr, SReg_128:$tlst,
- 0, 0, 0)
->;
-
/* int_SI_export */
def : Pat <
(int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
@@ -1506,7 +1503,7 @@ def : Pat <
// 3. Offset in an 32Bit VGPR
def : Pat <
(int_SI_load_const SReg_128:$sbase, VReg_32:$voff),
- (BUFFER_LOAD_DWORD 0, 1, 0, 0, 0, 0, VReg_32:$voff, SReg_128:$sbase, 0, 0, 0)
+ (BUFFER_LOAD_DWORD 0, SReg_128:$sbase, VReg_32:$voff)
>;
/********** ================== **********/
--
1.7.3.4
-------------- next part --------------
>From 13ca05adac8ccc1920381a78e39141d80aebcbd5 Mon Sep 17 00:00:00 2001
From: Tom Stellard <thomas.stellard at amd.com>
Date: Mon, 4 Mar 2013 15:12:16 -0500
Subject: [PATCH 6/6] R600/SI: Add support for buffer stores v2
v2:
- Use the ADDR64 bit
---
lib/Target/R600/AMDGPUCallingConv.td | 8 +++++++-
lib/Target/R600/AMDGPUISelLowering.h | 1 +
lib/Target/R600/AMDILISelDAGToDAG.cpp | 23 +++++++++++++++++++++++
lib/Target/R600/SIISelLowering.cpp | 32 ++++++++++++++++++++++++++++++++
lib/Target/R600/SIISelLowering.h | 1 +
lib/Target/R600/SIInstrInfo.td | 26 ++++++++++++++++++++++++++
lib/Target/R600/SIInstructions.td | 10 ++++++++--
lib/Target/R600/SIRegisterInfo.td | 2 +-
test/CodeGen/R600/imm.ll | 3 ---
test/CodeGen/R600/store.ll | 11 +++++++++++
10 files changed, 110 insertions(+), 7 deletions(-)
create mode 100644 test/CodeGen/R600/store.ll
diff --git a/lib/Target/R600/AMDGPUCallingConv.td b/lib/Target/R600/AMDGPUCallingConv.td
index 45ae37e..9c30515 100644
--- a/lib/Target/R600/AMDGPUCallingConv.td
+++ b/lib/Target/R600/AMDGPUCallingConv.td
@@ -32,8 +32,14 @@ def CC_SI : CallingConv<[
VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31
- ]>>>
+ ]>>>,
+ // This is the default for i64 values.
+ // XXX: We should change this once clang understands the CC_AMDGPU.
+ CCIfType<[i64], CCAssignToRegWithShadow<
+ [ SGPR0, SGPR2, SGPR4, SGPR6, SGPR8, SGPR10, SGPR12, SGPR14 ],
+ [ SGPR1, SGPR3, SGPR5, SGPR7, SGPR9, SGPR11, SGPR13, SGPR15 ]
+ >>
]>;
def CC_AMDGPU : CallingConv<[
diff --git a/lib/Target/R600/AMDGPUISelLowering.h b/lib/Target/R600/AMDGPUISelLowering.h
index f31b646..c2a79ea 100644
--- a/lib/Target/R600/AMDGPUISelLowering.h
+++ b/lib/Target/R600/AMDGPUISelLowering.h
@@ -116,6 +116,7 @@ enum {
BRANCH_COND,
// End AMDIL ISD Opcodes
BITALIGN,
+ BUFFER_STORE,
DWORDADDR,
FRACT,
FMAX,
diff --git a/lib/Target/R600/AMDILISelDAGToDAG.cpp b/lib/Target/R600/AMDILISelDAGToDAG.cpp
index fa8f62d..e0e0482 100644
--- a/lib/Target/R600/AMDILISelDAGToDAG.cpp
+++ b/lib/Target/R600/AMDILISelDAGToDAG.cpp
@@ -191,6 +191,29 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
RegSeqArgs, 2 * N->getNumOperands() + 1);
}
+ case ISD::BUILD_PAIR: {
+ SDValue RC, SubReg0, SubReg1;
+ const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
+ if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
+ break;
+ }
+ if (N->getValueType(0) == MVT::i128) {
+ RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32);
+ SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, MVT::i32);
+ SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32);
+ } else if (N->getValueType(0) == MVT::i64) {
+ RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32);
+ SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
+ SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
+ } else {
+ llvm_unreachable("Unhandled value type for BUILD_PAIR");
+ }
+ const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
+ N->getOperand(1), SubReg1 };
+ return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
+ N->getDebugLoc(), N->getValueType(0), Ops, 5);
+ }
+
case ISD::ConstantFP:
case ISD::Constant: {
const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
index 7fa28d9..ef0df9e 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -49,6 +49,7 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
addRegisterClass(MVT::v4i32, &AMDGPU::VReg_128RegClass);
addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
+ addRegisterClass(MVT::i128, &AMDGPU::SReg_128RegClass);
addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
@@ -70,6 +71,10 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
+
+ setOperationAction(ISD::STORE, MVT::i32, Custom);
+ setOperationAction(ISD::STORE, MVT::i64, Custom);
+
setTargetDAGCombine(ISD::SELECT_CC);
setTargetDAGCombine(ISD::SETCC);
@@ -234,6 +239,7 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
case ISD::BRCOND: return LowerBRCOND(Op, DAG);
case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
+ case ISD::STORE: return LowerSTORE(Op, DAG);
}
return SDValue();
}
@@ -332,6 +338,32 @@ SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
return Chain;
}
+#define RSRC_DATA_FORMAT 0xf00000000000
+
+SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
+ StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
+ SDValue Chain = Op.getOperand(0);
+ SDValue Value = Op.getOperand(1);
+ SDValue VirtualAddress = Op.getOperand(2);
+ DebugLoc DL = Op.getDebugLoc();
+
+ if (StoreNode->getAddressSpace() != AMDGPUAS::GLOBAL_ADDRESS) {
+ return SDValue();
+ }
+
+ SDValue SrcSrc = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i128,
+ DAG.getConstant(0, MVT::i64),
+ DAG.getConstant(RSRC_DATA_FORMAT, MVT::i64));
+
+ SDValue Ops[2];
+ Ops[0] = DAG.getNode(AMDGPUISD::BUFFER_STORE, DL, MVT::Other, Chain,
+ Value, SrcSrc, VirtualAddress);
+ Ops[1] = Chain;
+
+ return DAG.getMergeValues(Ops, 2, DL);
+
+}
+
SDValue SITargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1);
diff --git a/lib/Target/R600/SIISelLowering.h b/lib/Target/R600/SIISelLowering.h
index 5ad2f40..ace32f8 100644
--- a/lib/Target/R600/SIISelLowering.h
+++ b/lib/Target/R600/SIISelLowering.h
@@ -24,6 +24,7 @@ class SITargetLowering : public AMDGPUTargetLowering {
const SIInstrInfo * TII;
const TargetRegisterInfo * TRI;
+ SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
index 6df2797..7fe3d86 100644
--- a/lib/Target/R600/SIInstrInfo.td
+++ b/lib/Target/R600/SIInstrInfo.td
@@ -26,6 +26,10 @@ def HI32 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
}]>;
+def SIbuffer_store : SDNode<"AMDGPUISD::BUFFER_STORE",
+ SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
+ [SDNPHasChain, SDNPMayStore]>;
+
def IMM8bitDWORD : ImmLeaf <
i32, [{
return (Imm & ~0x3FC) == 0;
@@ -305,6 +309,28 @@ class MUBUF_Load_Helper <bits<7> op, string name, RegisterClass regClass,
let soffset = 128; // ZERO
}
+class MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
+ ValueType VT> :
+ MUBUF <op, (outs), (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr),
+ name#" $vdata, $srsrc + $vaddr",
+ [(SIbuffer_store (VT vdataClass:$vdata), (i128 SReg_128:$srsrc),
+ (i64 VReg_64:$vaddr))]> {
+
+ let mayLoad = 0;
+ let mayStore = 1;
+
+ // Encoding
+ let offset = 0;
+ let offen = 0;
+ let idxen = 0;
+ let glc = 0;
+ let addr64 = 1;
+ let lds = 0;
+ let slc = 0;
+ let tfe = 0;
+ let soffset = 128; // ZERO
+}
+
class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
op,
(outs regClass:$dst),
diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
index bbe035a..34396e3 100644
--- a/lib/Target/R600/SIInstructions.td
+++ b/lib/Target/R600/SIInstructions.td
@@ -414,8 +414,14 @@ def BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2",
def BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128, []>;
//def BUFFER_STORE_BYTE : MUBUF_ <0x00000018, "BUFFER_STORE_BYTE", []>;
//def BUFFER_STORE_SHORT : MUBUF_ <0x0000001a, "BUFFER_STORE_SHORT", []>;
-//def BUFFER_STORE_DWORD : MUBUF_ <0x0000001c, "BUFFER_STORE_DWORD", []>;
-//def BUFFER_STORE_DWORDX2 : MUBUF_DWORDX2 <0x0000001d, "BUFFER_STORE_DWORDX2", []>;
+
+def BUFFER_STORE_DWORD : MUBUF_Store_Helper <
+ 0x0000001c, "BUFFER_STORE_DWORD", VReg_32, i32
+>;
+
+def BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper <
+ 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64, i64
+>;
//def BUFFER_STORE_DWORDX4 : MUBUF_DWORDX4 <0x0000001e, "BUFFER_STORE_DWORDX4", []>;
//def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>;
//def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>;
diff --git a/lib/Target/R600/SIRegisterInfo.td b/lib/Target/R600/SIRegisterInfo.td
index 4f14931..2c10107 100644
--- a/lib/Target/R600/SIRegisterInfo.td
+++ b/lib/Target/R600/SIRegisterInfo.td
@@ -151,7 +151,7 @@ def SReg_64 : RegisterClass<"AMDGPU", [i64, i1], 64,
(add SGPR_64, VCCReg, EXECReg)
>;
-def SReg_128 : RegisterClass<"AMDGPU", [v16i8], 128, (add SGPR_128)>;
+def SReg_128 : RegisterClass<"AMDGPU", [v16i8, i128], 128, (add SGPR_128)>;
def SReg_256 : RegisterClass<"AMDGPU", [v32i8], 256, (add SGPR_256)>;
diff --git a/test/CodeGen/R600/imm.ll b/test/CodeGen/R600/imm.ll
index 02b7309..979efb0 100644
--- a/test/CodeGen/R600/imm.ll
+++ b/test/CodeGen/R600/imm.ll
@@ -1,8 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
-; XXX: Enable once SI supports buffer stores
-; XFAIL: *
-
; Use a 64-bit value with lo bits that can be represented as an inline constant
; CHECK: @i64_imm_inline_lo
; CHECK: S_MOV_B32 [[LO:SGPR[0-9]+]], 5
diff --git a/test/CodeGen/R600/store.ll b/test/CodeGen/R600/store.ll
new file mode 100644
index 0000000..4382bff
--- /dev/null
+++ b/test/CodeGen/R600/store.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
+
+; CHECK: @store_float
+; EG-CHECK: RAT_WRITE_CACHELESS_32_eg T{{[0-9]+\.X, T[0-9]+\.X}}, 1
+; SI-CHECK: BUFFER_STORE_DWORD
+
+define void @store_float(float addrspace(1)* %out, float %in) {
+ store float %in, float addrspace(1)* %out
+ ret void
+}
--
1.7.3.4
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