[llvm] r178417 - [NVPTX] Remove support for SM < 2.0. This was never fully supported anyway.
Justin Holewinski
jholewinski at nvidia.com
Sat Mar 30 07:29:30 PDT 2013
Author: jholewinski
Date: Sat Mar 30 09:29:30 2013
New Revision: 178417
URL: http://llvm.org/viewvc/llvm-project?rev=178417&view=rev
Log:
[NVPTX] Remove support for SM < 2.0. This was never fully supported anyway.
Removed:
llvm/trunk/test/CodeGen/NVPTX/arithmetic-fp-sm10.ll
llvm/trunk/test/CodeGen/NVPTX/convert-int-sm10.ll
llvm/trunk/test/CodeGen/NVPTX/sm-version-10.ll
llvm/trunk/test/CodeGen/NVPTX/sm-version-11.ll
llvm/trunk/test/CodeGen/NVPTX/sm-version-12.ll
llvm/trunk/test/CodeGen/NVPTX/sm-version-13.ll
Modified:
llvm/trunk/lib/Target/NVPTX/NVPTX.td
llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.cpp
llvm/trunk/test/CodeGen/NVPTX/annotations.ll
llvm/trunk/test/CodeGen/NVPTX/arithmetic-int.ll
llvm/trunk/test/CodeGen/NVPTX/calling-conv.ll
llvm/trunk/test/CodeGen/NVPTX/compare-int.ll
llvm/trunk/test/CodeGen/NVPTX/convert-fp.ll
llvm/trunk/test/CodeGen/NVPTX/intrinsic-old.ll
llvm/trunk/test/CodeGen/NVPTX/intrinsics.ll
llvm/trunk/test/CodeGen/NVPTX/ld-addrspace.ll
llvm/trunk/test/CodeGen/NVPTX/st-addrspace.ll
llvm/trunk/test/CodeGen/NVPTX/tuple-literal.ll
Modified: llvm/trunk/lib/Target/NVPTX/NVPTX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTX.td?rev=178417&r1=178416&r2=178417&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTX.td (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTX.td Sat Mar 30 09:29:30 2013
@@ -26,14 +26,6 @@ include "NVPTXInstrInfo.td"
//===----------------------------------------------------------------------===//
// SM Versions
-def SM10 : SubtargetFeature<"sm_10", "SmVersion", "10",
- "Target SM 1.0">;
-def SM11 : SubtargetFeature<"sm_11", "SmVersion", "11",
- "Target SM 1.1">;
-def SM12 : SubtargetFeature<"sm_12", "SmVersion", "12",
- "Target SM 1.2">;
-def SM13 : SubtargetFeature<"sm_13", "SmVersion", "13",
- "Target SM 1.3">;
def SM20 : SubtargetFeature<"sm_20", "SmVersion", "20",
"Target SM 2.0">;
def SM21 : SubtargetFeature<"sm_21", "SmVersion", "21",
@@ -56,10 +48,6 @@ def PTX31 : SubtargetFeature<"ptx31", "P
class Proc<string Name, list<SubtargetFeature> Features>
: Processor<Name, NoItineraries, Features>;
-def : Proc<"sm_10", [SM10]>;
-def : Proc<"sm_11", [SM11]>;
-def : Proc<"sm_12", [SM12]>;
-def : Proc<"sm_13", [SM13]>;
def : Proc<"sm_20", [SM20]>;
def : Proc<"sm_21", [SM21]>;
def : Proc<"sm_30", [SM30]>;
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.cpp?rev=178417&r1=178416&r2=178417&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.cpp Sat Mar 30 09:29:30 2013
@@ -33,12 +33,12 @@ cl::opt<NVPTX::DrvInterface> DriverInter
NVPTXSubtarget::NVPTXSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool is64Bit)
: NVPTXGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit), PTXVersion(0),
- SmVersion(10) {
+ SmVersion(20) {
drvInterface = DriverInterface;
// Provide the default CPU if none
- std::string defCPU = "sm_10";
+ std::string defCPU = "sm_20";
ParseSubtargetFeatures((CPU.empty() ? defCPU : CPU), FS);
Modified: llvm/trunk/test/CodeGen/NVPTX/annotations.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/annotations.ll?rev=178417&r1=178416&r2=178417&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/annotations.ll (original)
+++ llvm/trunk/test/CodeGen/NVPTX/annotations.ll Sat Mar 30 09:29:30 2013
@@ -1,5 +1,3 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
Removed: llvm/trunk/test/CodeGen/NVPTX/arithmetic-fp-sm10.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/arithmetic-fp-sm10.ll?rev=178416&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/arithmetic-fp-sm10.ll (original)
+++ llvm/trunk/test/CodeGen/NVPTX/arithmetic-fp-sm10.ll (removed)
@@ -1,72 +0,0 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s
-
-;; These tests should run for all targets
-
-;;===-- Basic instruction selection tests ---------------------------------===;;
-
-
-;;; f64
-
-define double @fadd_f64(double %a, double %b) {
-; CHECK: add.f64 %fl{{[0-9]+}}, %fl{{[0-9]+}}, %fl{{[0-9]+}}
-; CHECK: ret
- %ret = fadd double %a, %b
- ret double %ret
-}
-
-define double @fsub_f64(double %a, double %b) {
-; CHECK: sub.f64 %fl{{[0-9]+}}, %fl{{[0-9]+}}, %fl{{[0-9]+}}
-; CHECK: ret
- %ret = fsub double %a, %b
- ret double %ret
-}
-
-define double @fmul_f64(double %a, double %b) {
-; CHECK: mul.f64 %fl{{[0-9]+}}, %fl{{[0-9]+}}, %fl{{[0-9]+}}
-; CHECK: ret
- %ret = fmul double %a, %b
- ret double %ret
-}
-
-define double @fdiv_f64(double %a, double %b) {
-; CHECK: div.rn.f64 %fl{{[0-9]+}}, %fl{{[0-9]+}}, %fl{{[0-9]+}}
-; CHECK: ret
- %ret = fdiv double %a, %b
- ret double %ret
-}
-
-;; PTX does not have a floating-point rem instruction
-
-
-;;; f32
-
-define float @fadd_f32(float %a, float %b) {
-; CHECK: add.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}
-; CHECK: ret
- %ret = fadd float %a, %b
- ret float %ret
-}
-
-define float @fsub_f32(float %a, float %b) {
-; CHECK: sub.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}
-; CHECK: ret
- %ret = fsub float %a, %b
- ret float %ret
-}
-
-define float @fmul_f32(float %a, float %b) {
-; CHECK: mul.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}
-; CHECK: ret
- %ret = fmul float %a, %b
- ret float %ret
-}
-
-define float @fdiv_f32(float %a, float %b) {
-; CHECK: div.full.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}
-; CHECK: ret
- %ret = fdiv float %a, %b
- ret float %ret
-}
-
-;; PTX does not have a floating-point rem instruction
Modified: llvm/trunk/test/CodeGen/NVPTX/arithmetic-int.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/arithmetic-int.ll?rev=178417&r1=178416&r2=178417&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/arithmetic-int.ll (original)
+++ llvm/trunk/test/CodeGen/NVPTX/arithmetic-int.ll Sat Mar 30 09:29:30 2013
@@ -1,5 +1,3 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
Modified: llvm/trunk/test/CodeGen/NVPTX/calling-conv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/calling-conv.ll?rev=178417&r1=178416&r2=178417&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/calling-conv.ll (original)
+++ llvm/trunk/test/CodeGen/NVPTX/calling-conv.ll Sat Mar 30 09:29:30 2013
@@ -1,5 +1,3 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
Modified: llvm/trunk/test/CodeGen/NVPTX/compare-int.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/compare-int.ll?rev=178417&r1=178416&r2=178417&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/compare-int.ll (original)
+++ llvm/trunk/test/CodeGen/NVPTX/compare-int.ll Sat Mar 30 09:29:30 2013
@@ -1,5 +1,3 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
Modified: llvm/trunk/test/CodeGen/NVPTX/convert-fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/convert-fp.ll?rev=178417&r1=178416&r2=178417&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/convert-fp.ll (original)
+++ llvm/trunk/test/CodeGen/NVPTX/convert-fp.ll Sat Mar 30 09:29:30 2013
@@ -1,5 +1,3 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
Removed: llvm/trunk/test/CodeGen/NVPTX/convert-int-sm10.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/convert-int-sm10.ll?rev=178416&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/convert-int-sm10.ll (original)
+++ llvm/trunk/test/CodeGen/NVPTX/convert-int-sm10.ll (removed)
@@ -1,55 +0,0 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s
-
-
-; i16
-
-define i16 @cvt_i16_i32(i32 %x) {
-; CHECK: cvt.u16.u32 %rs{{[0-9]+}}, %r{{[0-9]+}}
-; CHECK: ret
- %a = trunc i32 %x to i16
- ret i16 %a
-}
-
-define i16 @cvt_i16_i64(i64 %x) {
-; CHECK: cvt.u16.u64 %rs{{[0-9]+}}, %rl{{[0-9]+}}
-; CHECK: ret
- %a = trunc i64 %x to i16
- ret i16 %a
-}
-
-
-
-; i32
-
-define i32 @cvt_i32_i16(i16 %x) {
-; CHECK: cvt.u32.u16 %r{{[0-9]+}}, %rs{{[0-9]+}}
-; CHECK: ret
- %a = zext i16 %x to i32
- ret i32 %a
-}
-
-define i32 @cvt_i32_i64(i64 %x) {
-; CHECK: cvt.u32.u64 %r{{[0-9]+}}, %rl{{[0-9]+}}
-; CHECK: ret
- %a = trunc i64 %x to i32
- ret i32 %a
-}
-
-
-
-; i64
-
-define i64 @cvt_i64_i16(i16 %x) {
-; CHECK: cvt.u64.u16 %rl{{[0-9]+}}, %rs{{[0-9]+}}
-; CHECK: ret
- %a = zext i16 %x to i64
- ret i64 %a
-}
-
-define i64 @cvt_i64_i32(i32 %x) {
-; CHECK: cvt.u64.u32 %rl{{[0-9]+}}, %r{{[0-9]+}}
-; CHECK: ret
- %a = zext i32 %x to i64
- ret i64 %a
-}
Modified: llvm/trunk/test/CodeGen/NVPTX/intrinsic-old.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/intrinsic-old.ll?rev=178417&r1=178416&r2=178417&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/intrinsic-old.ll (original)
+++ llvm/trunk/test/CodeGen/NVPTX/intrinsic-old.ll Sat Mar 30 09:29:30 2013
@@ -1,5 +1,3 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
Modified: llvm/trunk/test/CodeGen/NVPTX/intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/intrinsics.ll?rev=178417&r1=178416&r2=178417&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/NVPTX/intrinsics.ll Sat Mar 30 09:29:30 2013
@@ -1,5 +1,3 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
Modified: llvm/trunk/test/CodeGen/NVPTX/ld-addrspace.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/ld-addrspace.ll?rev=178417&r1=178416&r2=178417&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/ld-addrspace.ll (original)
+++ llvm/trunk/test/CodeGen/NVPTX/ld-addrspace.ll Sat Mar 30 09:29:30 2013
@@ -1,6 +1,4 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s --check-prefix=PTX32
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=PTX32
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s --check-prefix=PTX64
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64
Removed: llvm/trunk/test/CodeGen/NVPTX/sm-version-10.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/sm-version-10.ll?rev=178416&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/sm-version-10.ll (original)
+++ llvm/trunk/test/CodeGen/NVPTX/sm-version-10.ll (removed)
@@ -1,6 +0,0 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s
-
-
-; CHECK: .target sm_10
-
Removed: llvm/trunk/test/CodeGen/NVPTX/sm-version-11.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/sm-version-11.ll?rev=178416&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/sm-version-11.ll (original)
+++ llvm/trunk/test/CodeGen/NVPTX/sm-version-11.ll (removed)
@@ -1,6 +0,0 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_11 | FileCheck %s
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_11 | FileCheck %s
-
-
-; CHECK: .target sm_11
-
Removed: llvm/trunk/test/CodeGen/NVPTX/sm-version-12.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/sm-version-12.ll?rev=178416&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/sm-version-12.ll (original)
+++ llvm/trunk/test/CodeGen/NVPTX/sm-version-12.ll (removed)
@@ -1,6 +0,0 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_12 | FileCheck %s
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_12 | FileCheck %s
-
-
-; CHECK: .target sm_12
-
Removed: llvm/trunk/test/CodeGen/NVPTX/sm-version-13.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/sm-version-13.ll?rev=178416&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/sm-version-13.ll (original)
+++ llvm/trunk/test/CodeGen/NVPTX/sm-version-13.ll (removed)
@@ -1,6 +0,0 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_13 | FileCheck %s
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_13 | FileCheck %s
-
-
-; CHECK: .target sm_13
-
Modified: llvm/trunk/test/CodeGen/NVPTX/st-addrspace.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/st-addrspace.ll?rev=178417&r1=178416&r2=178417&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/st-addrspace.ll (original)
+++ llvm/trunk/test/CodeGen/NVPTX/st-addrspace.ll Sat Mar 30 09:29:30 2013
@@ -1,6 +1,4 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s --check-prefix=PTX32
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=PTX32
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s --check-prefix=PTX64
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64
Modified: llvm/trunk/test/CodeGen/NVPTX/tuple-literal.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/tuple-literal.ll?rev=178417&r1=178416&r2=178417&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/tuple-literal.ll (original)
+++ llvm/trunk/test/CodeGen/NVPTX/tuple-literal.ll Sat Mar 30 09:29:30 2013
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_13
+; RUN: llc < %s -march=nvptx -mcpu=sm_20
define ptx_device void @test_function({i8, i8}*) {
ret void
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