[llvm] r178077 - Restore real bit lengths on PPC register numbers

Bill Schmidt wschmidt at linux.vnet.ibm.com
Tue Mar 26 19:11:12 PDT 2013


Thanks, Hal!

Bill

On Tue, 2013-03-26 at 21:50 +0000, Hal Finkel wrote:
> Author: hfinkel
> Date: Tue Mar 26 16:50:26 2013
> New Revision: 178077
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=178077&view=rev
> Log:
> Restore real bit lengths on PPC register numbers
> 
> As suggested by Bill Schmidt (in reviewing r178067), use the real register
> number bit lengths (which is self-documenting, and prevents using illegal
> numbers), and set only the relevant bits in HWEncoding (which defaults to 0).
> 
> No functionality change intended.
> 
> Modified:
>     llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td
> 
> Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td?rev=178077&r1=178076&r2=178077&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td Tue Mar 26 16:50:26 2013
> @@ -26,8 +26,8 @@ class PPCReg<string n> : Register<n> {
>  // We identify all our registers with a 5-bit ID, for consistency's sake.
> 
>  // GPR - One of the 32 32-bit general-purpose registers
> -class GPR<bits<16> num, string n> : PPCReg<n> {
> -  let HWEncoding = num;
> +class GPR<bits<5> num, string n> : PPCReg<n> {
> +  let HWEncoding{4-0} = num;
>  }
> 
>  // GP8 - One of the 32 64-bit general-purpose registers
> @@ -38,29 +38,29 @@ class GP8<GPR SubReg, string n> : PPCReg
>  }
> 
>  // SPR - One of the 32-bit special-purpose registers
> -class SPR<bits<16> num, string n> : PPCReg<n> {
> -  let HWEncoding = num;
> +class SPR<bits<10> num, string n> : PPCReg<n> {
> +  let HWEncoding{9-0} = num;
>  }
> 
>  // FPR - One of the 32 64-bit floating-point registers
> -class FPR<bits<16> num, string n> : PPCReg<n> {
> -  let HWEncoding = num;
> +class FPR<bits<5> num, string n> : PPCReg<n> {
> +  let HWEncoding{4-0} = num;
>  }
> 
>  // VR - One of the 32 128-bit vector registers
> -class VR<bits<16> num, string n> : PPCReg<n> {
> -  let HWEncoding = num;
> +class VR<bits<5> num, string n> : PPCReg<n> {
> +  let HWEncoding{4-0} = num;
>  }
> 
>  // CR - One of the 8 4-bit condition registers
> -class CR<bits<16> num, string n, list<Register> subregs> : PPCReg<n> {
> -  let HWEncoding = num;
> +class CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
> +  let HWEncoding{2-0} = num;
>    let SubRegs = subregs;
>  }
> 
>  // CRBIT - One of the 32 1-bit condition register fields
> -class CRBIT<bits<16> num, string n> : PPCReg<n> {
> -  let HWEncoding = num;
> +class CRBIT<bits<5> num, string n> : PPCReg<n> {
> +  let HWEncoding{4-0} = num;
>  }
> 
>  // General-purpose registers
> 
> 
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