[llvm] r178049 - Annotate control instructions with SchedRW lists.
Andrew Trick
atrick at apple.com
Tue Mar 26 15:38:42 PDT 2013
On Mar 26, 2013, at 11:24 AM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
> Author: stoklund
> Date: Tue Mar 26 13:24:17 2013
> New Revision: 178049
>
> URL: http://llvm.org/viewvc/llvm-project?rev=178049&view=rev
> Log:
> Annotate control instructions with SchedRW lists.
>
> This could definitely be more granular. I am not sure if it makes a
> difference.
>
> Modified:
> llvm/trunk/lib/Target/X86/X86InstrControl.td
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrControl.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrControl.td?rev=178049&r1=178048&r2=178049&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrControl.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrControl.td Tue Mar 26 13:24:17 2013
> @@ -20,7 +20,7 @@
> // The X86retflag return instructions are variadic because we may add ST0 and
> // ST1 arguments when returning values on the x87 stack.
> let isTerminator = 1, isReturn = 1, isBarrier = 1,
> - hasCtrlDep = 1, FPForm = SpecialFP in {
> + hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
For SchedWrites that don't match def operands, we don't *have* to call them "Writes". That name only indicates that they must be ordered with respect to other Writes that do match def operands. And I haven't thought of a better scheduler-specific prefix.
-Andy
> def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
> "ret",
> [(X86retflag 0)], IIC_RET>;
> @@ -46,7 +46,7 @@ let isTerminator = 1, isReturn = 1, isBa
> }
>
> // Unconditional branches.
> -let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
> +let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
> def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
> "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>;
> def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
> @@ -58,7 +58,7 @@ let isBarrier = 1, isBranch = 1, isTermi
> }
>
> // Conditional Branches.
> -let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
> +let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in {
> multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
> def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, [],
> IIC_Jcc>;
> @@ -85,7 +85,7 @@ defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst",
> defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
>
> // jcx/jecx/jrcx instructions.
> -let isBranch = 1, isTerminator = 1 in {
> +let isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
> // These are the 32-bit versions of this instruction for the asmparser. In
> // 32-bit mode, the address size prefix is jcxz and the unprefixed version is
> // jecxz.
> @@ -110,36 +110,46 @@ let isBranch = 1, isTerminator = 1 in {
> // Indirect branches
> let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
> def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
> - [(brind GR32:$dst)], IIC_JMP_REG>, Requires<[In32BitMode]>;
> + [(brind GR32:$dst)], IIC_JMP_REG>, Requires<[In32BitMode]>,
> + Sched<[WriteJump]>;
> def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
> - [(brind (loadi32 addr:$dst))], IIC_JMP_MEM>, Requires<[In32BitMode]>;
> + [(brind (loadi32 addr:$dst))], IIC_JMP_MEM>,
> + Requires<[In32BitMode]>, Sched<[WriteJumpLd]>;
>
> def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
> - [(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>;
> + [(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>,
> + Sched<[WriteJump]>;
> def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
> - [(brind (loadi64 addr:$dst))], IIC_JMP_MEM>, Requires<[In64BitMode]>;
> + [(brind (loadi64 addr:$dst))], IIC_JMP_MEM>,
> + Requires<[In64BitMode]>, Sched<[WriteJumpLd]>;
>
> def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
> (ins i16imm:$off, i16imm:$seg),
> - "ljmp{w}\t{$seg, $off|$off, $seg}", [], IIC_JMP_FAR_PTR>, OpSize;
> + "ljmp{w}\t{$seg, $off|$off, $seg}", [],
> + IIC_JMP_FAR_PTR>, OpSize, Sched<[WriteJump]>;
> def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
> (ins i32imm:$off, i16imm:$seg),
> - "ljmp{l}\t{$seg, $off|$off, $seg}", [], IIC_JMP_FAR_PTR>;
> + "ljmp{l}\t{$seg, $off|$off, $seg}", [],
> + IIC_JMP_FAR_PTR>, Sched<[WriteJump]>;
> def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
> - "ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>;
> + "ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>,
> + Sched<[WriteJump]>;
>
> def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
> - "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize;
> + "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize,
> + Sched<[WriteJumpLd]>;
> def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
> - "ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>;
> + "ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>,
> + Sched<[WriteJumpLd]>;
> }
>
>
> // Loop instructions
> -
> +let SchedRW = [WriteJump] in {
> def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", [], IIC_LOOP>;
> def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", [], IIC_LOOPE>;
> def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", [], IIC_LOOPNE>;
> +}
>
> //===----------------------------------------------------------------------===//
> // Call Instructions...
> @@ -152,27 +162,31 @@ let isCall = 1 in
> let Uses = [ESP] in {
> def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
> (outs), (ins i32imm_pcrel:$dst),
> - "call{l}\t$dst", [], IIC_CALL_RI>, Requires<[In32BitMode]>;
> + "call{l}\t$dst", [], IIC_CALL_RI>,
> + Requires<[In32BitMode]>, Sched<[WriteJump]>;
> def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
> "call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>,
> - Requires<[In32BitMode]>;
> + Requires<[In32BitMode]>, Sched<[WriteJump]>;
> def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),
> - "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))], IIC_CALL_MEM>,
> - Requires<[In32BitMode]>;
> + "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))],
> + IIC_CALL_MEM>,
> + Requires<[In32BitMode]>, Sched<[WriteJumpLd]>;
>
> def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
> (ins i16imm:$off, i16imm:$seg),
> "lcall{w}\t{$seg, $off|$off, $seg}", [],
> - IIC_CALL_FAR_PTR>, OpSize;
> + IIC_CALL_FAR_PTR>, OpSize, Sched<[WriteJump]>;
> def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
> (ins i32imm:$off, i16imm:$seg),
> "lcall{l}\t{$seg, $off|$off, $seg}", [],
> - IIC_CALL_FAR_PTR>;
> + IIC_CALL_FAR_PTR>, Sched<[WriteJump]>;
>
> def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
> - "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize;
> + "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize,
> + Sched<[WriteJumpLd]>;
> def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
> - "lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>;
> + "lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>,
> + Sched<[WriteJumpLd]>;
>
> // callw for 16 bit code for the assembler.
> let isAsmParserOnly = 1 in
> @@ -185,7 +199,7 @@ let isCall = 1 in
> // Tail call stuff.
>
> let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
> - isCodeGenOnly = 1 in
> + isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in
> let Uses = [ESP] in {
> def TCRETURNdi : PseudoI<(outs),
> (ins i32imm_pcrel:$dst, i32imm:$offset), []>;
> @@ -216,7 +230,7 @@ let isCall = 1, isTerminator = 1, isRetu
> // RSP is marked as a use to prevent stack-pointer assignments that appear
> // immediately before calls from potentially appearing dead. Uses for argument
> // registers are added manually.
> -let isCall = 1, Uses = [RSP] in {
> +let isCall = 1, Uses = [RSP], SchedRW = [WriteJump] in {
> // NOTE: this pattern doesn't match "X86call imm", because we do not know
> // that the offset between an arbitrary immediate and the call will fit in
> // the 32-bit pcrel field that we have.
> @@ -245,13 +259,12 @@ let isCall = 1, isCodeGenOnly = 1 in
> def W64ALLOCA : Ii32PCRel<0xE8, RawFrm,
> (outs), (ins i64i32imm_pcrel:$dst),
> "call{q}\t$dst", [], IIC_CALL_RI>,
> - Requires<[IsWin64]>;
> + Requires<[IsWin64]>, Sched<[WriteJump]>;
> }
>
> let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
> - isCodeGenOnly = 1 in
> - let Uses = [RSP],
> - usesCustomInserter = 1 in {
> + isCodeGenOnly = 1, Uses = [RSP], usesCustomInserter = 1,
> + SchedRW = [WriteJump] in {
> def TCRETURNdi64 : PseudoI<(outs),
> (ins i64i32imm_pcrel:$dst, i32imm:$offset),
> []>;
>
>
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