[llvm] r177968 - ARM Scheduler Model: Add resources instructions, map resources in subtargets

[Andrew Trick]

On Mar 25, 2013, at 7:01 PM, Arnold Schwaighofer <aschwaighofer at apple.com> wrote:
> Author: arnolds
> Date: Mon Mar 25 21:01:42 2013
> New Revision: 177968
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=177968&view=rev
> Log:
> ARM Scheduler Model: Add resources instructions, map resources in subtargets
> 
> Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define
> resource mappings under the CortexA9 SchedModel. Define resources and mappings
> for the SwiftModel.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>    llvm/trunk/lib/Target/ARM/ARMSchedule.td
>    llvm/trunk/lib/Target/ARM/ARMScheduleA9.td
>    llvm/trunk/lib/Target/ARM/ARMScheduleSwift.td
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=177968&r1=177967&r2=177968&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Mar 25 21:01:42 2013
> @@ -1010,7 +1010,8 @@ multiclass AsI1_bin_irs<bits<4> opcod, s
>   let isReMaterializable = 1 in {
>   def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
>                iii, opc, "\t$Rd, $Rn, $imm",
> -               [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
> +               [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
> +           Sched<[WriteALU, ReadAdvanceALU]> {

You don't need to call the operand's Read type an "Advance". I would just do:
[WriteALU, ReadALU]

> Modified: llvm/trunk/lib/Target/ARM/ARMSchedule.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSchedule.td?rev=177968&r1=177967&r2=177968&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMSchedule.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMSchedule.td Mon Mar 25 21:01:42 2013
> @@ -64,6 +64,13 @@ def WriteALUsr : SchedWrite; // Shift by
> def WriteALUSsr : SchedWrite; // Shift by register (flag setting).
> def ReadAdvanceALUsr : SchedRead; // Some operands are read later.
> 
> +// Define TII for use in SchedVariant Predicates.
> +def : PredicateProlog<[{
> +  const ARMBaseInstrInfo *TII =
> +    static_cast<const ARMBaseInstrInfo*>(SchedModel->getInstrInfo());
> +  (void)TII;
> +}]>;
> +
> //===----------------------------------------------------------------------===//
> // Instruction Itinerary classes used for ARM
> //
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA9.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td?rev=177968&r1=177967&r2=177968&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMScheduleA9.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMScheduleA9.td Mon Mar 25 21:01:42 2013
> @@ -1898,6 +1898,8 @@ def CortexA9Model : SchedMachineModel {
> //===----------------------------------------------------------------------===//
> // Define each kind of processor resource and number available.
> 
> +let SchedModel = CortexA9Model in {
> +
> def A9UnitALU : ProcResource<2>;
> def A9UnitMul : ProcResource<1> { let Super = A9UnitALU; }
> def A9UnitAGU : ProcResource<1>;
> @@ -2003,13 +2005,6 @@ foreach NumCycles = 2-8 in {
> def A9WriteCycle#NumCycles : WriteSequence<[A9WriteCycle1], NumCycles>;
> } // foreach NumCycles
> 
> -// Define TII for use in SchedVariant Predicates.
> -def : PredicateProlog<[{
> -  const ARMBaseInstrInfo *TII =
> -    static_cast<const ARMBaseInstrInfo*>(SchedModel->getInstrInfo());
> -  (void)TII;
> -}]>;
> -
> // Define address generation sequences and predicates for 8 flavors of LDMs.
> foreach NumAddr = 1-8 in {
> 
> @@ -2279,7 +2274,6 @@ def A9Read4 : SchedReadAdvance<3>;
> 
> // This table follows the ARM Cortex-A9 Technical Reference Manuals,
> // mostly in order.
> -let SchedModel = CortexA9Model in {
> 
> def :ItinRW<[A9WriteI], [IIC_iMOVi,IIC_iMOVr,IIC_iMOVsi,
>                          IIC_iMVNi,IIC_iMVNsi,
> @@ -2486,4 +2480,13 @@ def :ItinRW<[A9WriteV9, A9Read3, A9Read2
> def :ItinRW<[A9WriteV10, A9Read3, A9Read2], [IIC_VMACQ, IIC_VFMACQ]>;
> def :ItinRW<[A9WriteV9, A9Read2, A9Read2], [IIC_VRECSD]>;
> def :ItinRW<[A9WriteV10, A9Read2, A9Read2], [IIC_VRECSQ]>;
> +
> +// New (incomplete) model mappings that don't rely on itinerary mappings.
> +def : SchedAlias<WriteALU, A9WriteA>;
> +def : SchedAlias<WriteALUsi, A9WriteAsi>;
> +def : SchedAlias<WriteALUsr, A9WriteAsr>;
> +def : SchedAlias<WriteALUSsr, A9WriteAsr>;
> +def : SchedAlias<ReadAdvanceALU, A9ReadA>;
> +def : SchedAlias<ReadAdvanceALUsr, A9ReadA>;

It's weird to define itineraries and SchedRW lists (and hopefully very temporary). So some hacking is fine. When the itineraries are removed, you'll end up with

def : WriteRes<WriteALU, [A9UnitALU]>;

So you could probably go straight to that and just rename existing A9WriteA references to WriteALU instead of using an alias.

> +
> } // SchedModel = CortexA9Model
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMScheduleSwift.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleSwift.td?rev=177968&r1=177967&r2=177968&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMScheduleSwift.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMScheduleSwift.td Mon Mar 25 21:01:42 2013
> @@ -1078,8 +1078,29 @@ def SwiftModel : SchedMachineModel {
>   let IssueWidth = 3; // 3 micro-ops are dispatched per cycle.
>   let MinLatency = 0; // Data dependencies are allowed within dispatch groups.
>   let LoadLatency = 3;
> +  let MispredictPenalty = 14; // A branch direction mispredict.
> 
>   let Itineraries = SwiftItineraries;
> }
> 
> -// TODO: Add Swift processor and scheduler resources.
> +// Swift resource mapping.
> +let SchedModel = SwiftModel in {
> +  // Processor resources.
> +  def SwiftUnitP01 : ProcResource<2>; // ALU unit.
> +  def SwiftUnitP0 : ProcResource<1> { let Super = SwiftUnitP01; } // Mul unit.
> +  def SwiftUnitP1 : ProcResource<1> { let Super = SwiftUnitP01; } // Br unit.
> +  def SwiftUnitP2 : ProcResource<1>; // LS unit.
> +  def SwiftUnitDiv : ProcResource<1>;

It's entirely up to you if you want to name the functional units by their type or by port #. It comes down to the readability of the WriteRes defs.

-Andy

> +  // 4.2.4 Arithmetic and Logical.
> +  // ADC,ADD,NEG,RSB,RSC,SBC,SUB,ADR
> +  // AND,BIC, EOR,ORN,ORR
> +  // CLZ,RBIT,REV,REV16,REVSH,PKH
> +  // Single cycle.
> +  def : WriteRes<WriteALU, [SwiftUnitP01]>;
> +  def : WriteRes<WriteALUsi, [SwiftUnitP01]>;
> +  def : WriteRes<WriteALUsr, [SwiftUnitP01]>;
> +  def : WriteRes<WriteALUSsr, [SwiftUnitP01]>;
> +  def : ReadAdvance<ReadAdvanceALU, 0>;
> +  def : ReadAdvance<ReadAdvanceALUsr, 2>;
> +}
> 
> 
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