[llvm] r178002 - PowerPC: Simplify BLR pattern.

[Bill Schmidt]

Hi Uli,

We're probably going to need a real generic BLR soon enough.  Hal is
trying to make use of the "blr 20,31,$+4" version of the instruction.
Right now this is done the same way as the one you have, with explicit
BO and BI values.  Just a heads-up in case the parser has any trouble
with it.

Thanks,
Bill

On Tue, 2013-03-26 at 10:53 +0000, Ulrich Weigand wrote:
> Author: uweigand
> Date: Tue Mar 26 05:53:27 2013
> New Revision: 178002
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=178002&view=rev
> Log:
> PowerPC: Simplify BLR pattern.
> 
> The BLR pattern cannot be recognized by the asm parser in its current form.
> This complexity is due to an apparent attempt to enable conditional BLR
> variants.  However, none of those can ever be generated by current code;
> the pattern is only ever created using the default "pred" operand.
> 
> To simplify the pattern and allow it to be recognized by the parser,
> this commit removes those attempts at conditional BLR support.
> 
> When we later come back to actually add real conditional BLR, this
> should probably be done via a fully generic conditional branch pattern.
> 
> No change in generated code.
> 
> 
> Modified:
>     llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
>     llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h
>     llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
> 
> Modified: llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp?rev=178002&r1=178001&r2=178002&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp Tue Mar 26 05:53:27 2013
> @@ -115,7 +115,6 @@ void PPCInstPrinter::printPredicateOpera
> 
>    if (StringRef(Modifier) == "cc") {
>      switch ((PPC::Predicate)Code) {
> -    case PPC::PRED_ALWAYS: return; // Don't print anything for always.
>      case PPC::PRED_LT: O << "lt"; return;
>      case PPC::PRED_LE: O << "le"; return;
>      case PPC::PRED_EQ: O << "eq"; return;
> @@ -129,8 +128,6 @@ void PPCInstPrinter::printPredicateOpera
>    
>    assert(StringRef(Modifier) == "reg" &&
>           "Need to specify 'cc' or 'reg' as predicate op modifier!");
> -  // Don't print the register for 'always'.
> -  if (Code == PPC::PRED_ALWAYS) return;
>    printOperand(MI, OpNo+1, O);
>  }
> 
> 
> Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h?rev=178002&r1=178001&r2=178002&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h (original)
> +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h Tue Mar 26 05:53:27 2013
> @@ -25,7 +25,6 @@ namespace llvm {
>  namespace PPC {
>    /// Predicate - These are "(BI << 5) | BO"  for various predicates.
>    enum Predicate {
> -    PRED_ALWAYS = (0 << 5) | 20,
>      PRED_LT     = (0 << 5) | 12,
>      PRED_LE     = (1 << 5) |  4,
>      PRED_EQ     = (2 << 5) | 12,
> 
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=178002&r1=178001&r2=178002&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Tue Mar 26 05:53:27 2013
> @@ -396,11 +396,10 @@ def memr : Operand<iPTR> {
>    let MIOperandInfo = (ops ptr_rc:$ptrreg);
>  }
> 
> -// PowerPC Predicate operand.  20 = (0<<5)|20 = always, CR0 is a dummy reg
> -// that doesn't matter.
> -def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
> -                                     (ops (i32 20), (i32 zero_reg))> {
> +// PowerPC Predicate operand.
> +def pred : Operand<OtherVT> {
>    let PrintMethod = "printPredicateOperand";
> +  let MIOperandInfo = (ops i32imm:$bibo, CRRC:$reg);
>  }
> 
>  // Define PowerPC specific addressing mode.
> @@ -478,10 +477,9 @@ def RESTORE_CR : Pseudo<(outs CRRC:$cond
>                       "#RESTORE_CR", []>;
> 
>  let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
> -  let isCodeGenOnly = 1, isReturn = 1, Uses = [LR, RM] in
> -    def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
> -                          "b${p:cc}lr ${p:reg}", BrB, 
> -                          [(retflag)]>;
> +  let isReturn = 1, Uses = [LR, RM] in
> +    def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", BrB,
> +                           [(retflag)]>;
>    let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in
>      def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
>  }
> 
> 
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