[llvm] r177423 - Prepare to make r0 an allocatable register on PPC

[Hal Finkel]

----- Original Message -----
> From: "Jakob Stoklund Olesen" <stoklund at 2pi.dk>
> To: "Hal Finkel" <hfinkel at anl.gov>
> Cc: "Commit Messages and Patches for LLVM" <llvm-commits at cs.uiuc.edu>
> Sent: Tuesday, March 19, 2013 4:52:53 PM
> Subject: Re: [llvm] r177423 - Prepare to make r0 an allocatable register on PPC
> 
> 
> On Mar 19, 2013, at 2:39 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> 
> >> It is also possible that something weird is happening because you
> >> put
> >> the same ZERO register in GPRC and G8RC. Try with separate 32 and
> >> 64-bit ZERO registers.
> > 
> > I tried this, and it does not change anything. I still get these
> > odd copies.
> 
> It's PPCCTRLoops producing:
> 
> BB#5:
>     Predecessors according to CFG: BB#2
>         %vreg18<def> = COPY %vreg0; G8RC:%vreg18
>         GPRC_and_GPRC_NOR0:%vreg0
>         MTCTR8 %vreg18, %CTR8<imp-def>; G8RC:%vreg18
>     Successors according to CFG: BB#3
> 
> Bad code:
> 
>     unsigned CopyOp = (isPPC64 && SrcRC == GPRC) ?
>                         (unsigned) PPC::EXTSW_32_64 :
>                         (unsigned) TargetOpcode::COPY;
>  
> Use hasSubClassEq() instead of ==.

Fixed in r177679. Thanks again!

 -Hal

> 
> /jakob
> 
>