[llvm] r177679 - Fix a register-class comparison bug in PPCCTRLoops

[Hal Finkel]

Author: hfinkel
Date: Thu Mar 21 18:23:34 2013
New Revision: 177679

URL: http://llvm.org/viewvc/llvm-project?rev=177679&view=rev
Log:
Fix a register-class comparison bug in PPCCTRLoops

Thanks to Jakob for isolating the underlying problem from the
test case in r177423. The original commit had introduced
asymmetric copy operations, but these turned out to be a work-around
to the real problem (the use of == instead of hasSubClassEq in PPCCTRLoops).

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCCTRLoops.cpp
    llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
    llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
    llvm/trunk/test/CodeGen/PowerPC/asym-regclass-copy.ll

Modified: llvm/trunk/lib/Target/PowerPC/PPCCTRLoops.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCCTRLoops.cpp?rev=177679&r1=177678&r2=177679&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCCTRLoops.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCCTRLoops.cpp Thu Mar 21 18:23:34 2013
@@ -685,7 +685,7 @@ bool PPCCTRLoops::convertToCTRLoop(Machi
     const TargetRegisterClass *SrcRC =
       MF->getRegInfo().getRegClass(TripCount->getReg());
     CountReg = MF->getRegInfo().createVirtualRegister(RC);
-    unsigned CopyOp = (isPPC64 && SrcRC == GPRC) ?
+    unsigned CopyOp = (isPPC64 && GPRC->hasSubClassEq(SrcRC)) ?
                         (unsigned) PPC::EXTSW_32_64 :
                         (unsigned) TargetOpcode::COPY;
     BuildMI(*Preheader, InsertPos, dl,

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=177679&r1=177678&r2=177679&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Thu Mar 21 18:23:34 2013
@@ -366,15 +366,6 @@ def XOR8 : XForm_6<31, 316, (outs G8RC:$
                    "xor $rA, $rS, $rB", IntSimple,
                    [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
 
-// Moves between 32-bit and 64-bit registers (used for copy resolution
-// after register allocation).
-let isCodeGenOnly = 1 in {
-def OR8_32  : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB),
-                      "or $rA, $rS, $rB", IntSimple, []>;
-def OR_64   : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB),
-                      "or $rA, $rS, $rB", IntSimple, []>;
-}
-
 // Logical ops with immediate.
 def ANDIo8  : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
                       "andi. $dst, $src1, $src2", IntGeneral,

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=177679&r1=177678&r2=177679&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Thu Mar 21 18:23:34 2013
@@ -422,15 +422,6 @@ void PPCInstrInfo::copyPhysReg(MachineBa
     Opc = PPC::VOR;
   else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
     Opc = PPC::CROR;
-
-  // Asymmetric copies:
-
-  else if (PPC::GPRCRegClass.contains(DestReg) &&
-           PPC::G8RCRegClass.contains(SrcReg))
-    Opc = PPC::OR_64;
-  else if (PPC::G8RCRegClass.contains(DestReg) &&
-           PPC::GPRCRegClass.contains(SrcReg))
-    Opc = PPC::OR8_32;
   else
     llvm_unreachable("Impossible reg-to-reg copy");
 

Modified: llvm/trunk/test/CodeGen/PowerPC/asym-regclass-copy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/asym-regclass-copy.ll?rev=177679&r1=177678&r2=177679&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/asym-regclass-copy.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/asym-regclass-copy.ll Thu Mar 21 18:23:34 2013
@@ -2,7 +2,8 @@
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
-; This test triggers the use of the asymmetric OR8_32 copy pattern.
+; This tests that the GPRC/GPRC_NOR0 intersection subclass relationship with
+; GPRC is handled correctly. When it was not, this test would assert.
 
 @gen_random.last = external unnamed_addr global i64, align 8
 @.str = external unnamed_addr constant [4 x i8], align 1