[llvm] r177518 - pre-RA-sched: fix TargetOpcode usage

[Andrew Trick]

On Mar 20, 2013, at 8:48 AM, Christian König <christian.koenig at amd.com> wrote:

> I've reverted the commit for now.
> 
> The code is trivial incorrect, but fixing it causes X86 to generate more inefficient code.
> 
> Somebody with more knowledge of the code should take a look at it.

I'm trying to kill off the whole pass. Until then, it's incorrect but not unsafe and through random luck doing what we want. For now, I'm fine if someone want to just delete these conditions if it doesn't cause serious regressions.
-Andy

> Am 20.03.2013 16:04, schrieb Koenig, Christian:
>> Hi Justin,
>>  
>> Yeah, seeing that also. I usually don’t compile neither X86 nor AArch64 so I didn’t stumbled over it before committing (and the changes seemed trivial). Currently investigating into it.
>>  
>> Christian.
>>  
>> From: Justin Holewinski [mailto:justin.holewinski at gmail.com] 
>> Sent: Wednesday, March 20, 2013 3:47 PM
>> To: Koenig, Christian
>> Cc: llvm-commits
>> Subject: Re: [llvm] r177518 - pre-RA-sched: fix TargetOpcode usage
>>  
>> Hi Christian,
>> 
>> I'm seeing some test suite failures with this change on Linux x86_64:
>> 
>> Failing Tests (7):
>>     LLVM :: CodeGen/AArch64/func-calls.ll
>>     LLVM :: CodeGen/AArch64/sibling-call.ll
>>     LLVM :: CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll
>>     LLVM :: CodeGen/X86/avx-basic.ll
>>     LLVM :: CodeGen/X86/avx-shuffle.ll
>>     LLVM :: CodeGen/X86/lsr-loop-exit-cond.ll
>>     LLVM :: CodeGen/X86/shift-bmi2.ll
>>  
>> 
>> On Wed, Mar 20, 2013 at 9:49 AM, Christian Konig <christian.koenig at amd.com> wrote:
>> Author: ckoenig
>> Date: Wed Mar 20 08:49:22 2013
>> New Revision: 177518
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=177518&view=rev
>> Log:
>> pre-RA-sched: fix TargetOpcode usage
>> 
>> TargetOpcodes need to be treaded as Machine- and not ISD-Opcodes.
>> 
>> Signed-off-by: Christian König <christian.koenig at amd.com>
>> 
>> Modified:
>>     llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>> 
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=177518&r1=177517&r2=177518&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Wed Mar 20 08:49:22 2013
>> @@ -1894,12 +1894,15 @@ unsigned RegReductionPQBase::getNodePrio
>>      // CopyToReg should be close to its uses to facilitate coalescing and
>>      // avoid spilling.
>>      return 0;
>> -  if (Opc == TargetOpcode::EXTRACT_SUBREG ||
>> -      Opc == TargetOpcode::SUBREG_TO_REG ||
>> -      Opc == TargetOpcode::INSERT_SUBREG)
>> -    // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be
>> -    // close to their uses to facilitate coalescing.
>> -    return 0;
>> +  if (SU->getNode() && SU->getNode()->isMachineOpcode()) {
>> +    Opc = SU->getNode()->getMachineOpcode();
>> +    if (Opc == TargetOpcode::EXTRACT_SUBREG ||
>> +        Opc == TargetOpcode::SUBREG_TO_REG ||
>> +        Opc == TargetOpcode::INSERT_SUBREG)
>> +      // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be
>> +      // close to their uses to facilitate coalescing.
>> +      return 0;
>> +  }
>>    if (SU->NumSuccs == 0 && SU->NumPreds != 0)
>>      // If SU does not have a register use, i.e. it doesn't produce a value
>>      // that would be consumed (e.g. store), then it terminates a chain of
>> @@ -2585,12 +2588,15 @@ static bool canEnableCoalescing(SUnit *S
>>      // avoid spilling.
>>      return true;
>> 
>> -  if (Opc == TargetOpcode::EXTRACT_SUBREG ||
>> -      Opc == TargetOpcode::SUBREG_TO_REG ||
>> -      Opc == TargetOpcode::INSERT_SUBREG)
>> -    // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be
>> -    // close to their uses to facilitate coalescing.
>> -    return true;
>> +  if (SU->getNode() && SU->getNode()->isMachineOpcode()) {
>> +    Opc = SU->getNode()->getMachineOpcode();
>> +    if (Opc == TargetOpcode::EXTRACT_SUBREG ||
>> +        Opc == TargetOpcode::SUBREG_TO_REG ||
>> +        Opc == TargetOpcode::INSERT_SUBREG)
>> +      // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be
>> +      // close to their uses to facilitate coalescing.
>> +      return true;
>> +  }
>> 
>>    if (SU->NumPreds == 0 && SU->NumSuccs != 0)
>>      // If SU does not have a register def, schedule it close to its uses
>> 
>> 
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>> 
>> 
>> 
>> --
>> 
>> Thanks,
>>  
>> Justin Holewinski
>> 
>> 
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