[llvm] r177599 - Model prefetches and barriers as loads.

[Hal Finkel]

----- Original Message -----
> From: "Jakob Stoklund Olesen" <stoklund at 2pi.dk>
> To: llvm-commits at cs.uiuc.edu
> Sent: Wednesday, March 20, 2013 6:09:53 PM
> Subject: [llvm] r177599 - Model prefetches and barriers as loads.
> 
> Author: stoklund
> Date: Wed Mar 20 18:09:53 2013
> New Revision: 177599
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=177599&view=rev
> Log:
> Model prefetches and barriers as loads.
> 
> It's not yet clear if these instructions need a more careful model.

In my experience, modeling prefetches as reading and writing to their argument's address works pretty well (in that it keeps the prefetches ahead of the loads they're supposed to be prefetching, and keeps them after the last real write). One issue that we currently have is that the MMO attached to the prefetch thinks that the relevant address range only has size 1 (because the prefetch intrinsic takes an i8*), but it should really have the size of the (L1) cache line.

 -Hal

> 
> Modified:
>     llvm/trunk/lib/Target/X86/X86InstrSSE.td
> 
> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=177599&r1=177598&r2=177599&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Mar 20 18:09:53 2013
> @@ -3487,7 +3487,7 @@ def : Pat<(alignednontemporalstore (v2i6
>  //===----------------------------------------------------------------------===//
>  
>  // Prefetch intrinsic.
> -let Predicates = [HasSSE1] in {
> +let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
>  def PREFETCHT0   : I<0x18, MRM1m, (outs), (ins i8mem:$src),
>      "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32
>      1))],
>      IIC_SSE_PREFETCH>, TB;
> @@ -3502,6 +3502,8 @@ def PREFETCHNTA  : I<0x18, MRM0m, (outs)
>      IIC_SSE_PREFETCH>, TB;
>  }
>  
> +// FIXME: How should these memory instructions be modeled?
> +let SchedRW = [WriteLoad] in {
>  // Flush cache
>  def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
>                 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
> @@ -3521,6 +3523,7 @@ def LFENCE : I<0xAE, MRM_E8, (outs), (in
>  def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
>                 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
>                 TB, Requires<[HasSSE2]>;
> +} // SchedRW
>  
>  def : Pat<(X86SFence), (SFENCE)>;
>  def : Pat<(X86LFence), (LFENCE)>;
> 
> 
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