[llvm] r177423 - Prepare to make r0 an allocatable register on PPC

[Hal Finkel]

----- Original Message -----
> From: "Jakob Stoklund Olesen" <stoklund at 2pi.dk>
> To: "Hal Finkel" <hfinkel at anl.gov>
> Cc: "Commit Messages and Patches for LLVM" <llvm-commits at cs.uiuc.edu>
> Sent: Tuesday, March 19, 2013 5:38:39 PM
> Subject: Re: [llvm] r177423 - Prepare to make r0 an allocatable register on PPC
> 
> 
> On Mar 19, 2013, at 1:58 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>
> wrote:
> 
> > It is also possible that something weird is happening because you
> > put the same ZERO register in GPRC and G8RC. Try with separate 32
> > and 64-bit ZERO registers.
> 
> The shared ZERO register is causing TableGen to emit an intersection
> class:
> 
>   // G8RC_NOX0_and_GPRC_NOR0 Register Class...
>   const uint16_t G8RC_NOX0_and_GPRC_NOR0[] = {
>     PPC::ZERO,
>   };
> 
> I think it is better to reflect the super/sub-register structure of
> the other R and X registers.

I'll do that, and I'll fix up the CTRLoops pass. Thanks for looking at this!

 -Hal

> 
> /jakob
> 
>