[llvm] r177423 - Prepare to make r0 an allocatable register on PPC
Hal Finkel
hfinkel at anl.gov
Tue Mar 19 11:58:55 PDT 2013
----- Original Message -----
> From: "Hal Finkel" <hfinkel at anl.gov>
> To: llvm-commits at cs.uiuc.edu
> Sent: Tuesday, March 19, 2013 1:51:05 PM
> Subject: [llvm] r177423 - Prepare to make r0 an allocatable register on PPC
>
> Author: hfinkel
> Date: Tue Mar 19 13:51:05 2013
> New Revision: 177423
>
> URL: http://llvm.org/viewvc/llvm-project?rev=177423&view=rev
> Log:
> Prepare to make r0 an allocatable register on PPC
>
> Currently the PPC r0 register is unconditionally reserved. There are
> two reasons
> for this:
>
> 1. r0 is treated specially (as the constant 0) by certain
> instructions, and so
> cannot be used with those instructions as a regular register.
>
> 2. r0 is used as a temporary register in the CR-register spilling
> process
> (where, under some circumstances, we require two GPRs).
>
> This change addresses the first reason by introducing a restricted
> register
> class (without r0) for use by those instructions that treat r0
> specially. These
> register classes have a new pseudo-register, ZERO, which represents
> the r0-as-0
> use. This has the side benefit of making the existing target code
> simpler (and
> easier to understand), and will make it clear to the register
> allocator that
> uses of r0 as 0 don't conflict will real uses of the r0 register.
>
> Once the CR spilling code is improved, we'll be able to allocate r0.
>
> Adding these extra register classes, for some reason unclear to me,
> causes
> requests to the target to copy 32-bit registers to 64-bit registers.
> The
> resulting code seems correct (and causes no test-suite failures), and
> the new
> test case covers this new kind of asymmetric copy.
Jakob,
I'd appreciate some insight into why this happens. Specifically, if you run the test case with -debug, you'll see this:
********** EXPANDING POST-RA PSEUDO INSTRS **********
********** Function: main
real copy: %X3<def> = COPY %R29<kill>
replaced by: %X3<def> = OR8_32 %R29, %R29<kill>
%R3 is a subregister of %X3, and if %X3 is available than so is %R3, and I don't understand why it now wants to do this whereas it did not previously. Nevertheless, everything seems okay.
Thanks again,
Hal
>
> As r0 is still reserved, no functionality change intended.
>
> Added:
> llvm/trunk/test/CodeGen/PowerPC/asym-regclass-copy.ll
> Modified:
> llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
> llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
> llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
> llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=177423&r1=177422&r2=177423&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Mar 19
> 13:51:05 2013
> @@ -1031,8 +1031,7 @@ bool PPCTargetLowering::SelectAddressReg
> short Imm;
> if (isIntS16Immediate(CN, Imm)) {
> Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
> - Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 :
> PPC::R0,
> - CN->getValueType(0));
> + Base = DAG.getRegister(PPC::ZERO, CN->getValueType(0));
> return true;
> }
>
> @@ -1080,8 +1079,7 @@ bool PPCTargetLowering::SelectAddressReg
> }
>
> // Otherwise, do it the hard way, using R0 as the base register.
> - Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
> - N.getValueType());
> + Base = DAG.getRegister(PPC::ZERO, N.getValueType());
> Index = N;
> return true;
> }
> @@ -1143,8 +1141,7 @@ bool PPCTargetLowering::SelectAddressReg
> short Imm;
> if (isIntS16Immediate(CN, Imm)) {
> Disp = DAG.getTargetConstant((unsigned short)Imm >> 2,
> getPointerTy());
> - Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 :
> PPC::R0,
> - CN->getValueType(0));
> + Base = DAG.getRegister(PPC::ZERO, CN->getValueType(0));
> return true;
> }
>
> @@ -5753,7 +5750,7 @@ PPCTargetLowering::EmitPartwordAtomicBin
> // registers without caring whether they're 32 or 64, but here
> we're
> // doing actual arithmetic on the addresses.
> bool is64bit = PPCSubTarget.isPPC64();
> - unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0;
> + unsigned ZeroReg = PPC::ZERO;
>
> const BasicBlock *LLVM_BB = BB->getBasicBlock();
> MachineFunction *F = BB->getParent();
> @@ -6142,7 +6139,7 @@ PPCTargetLowering::EmitInstrWithCustomIn
> unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
> unsigned Ptr1Reg;
> unsigned TmpReg = RegInfo.createVirtualRegister(RC);
> - unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0;
> + unsigned ZeroReg = PPC::ZERO;
> // thisMBB:
> // ...
> // fallthrough --> loopMBB
> @@ -6631,6 +6628,9 @@ PPCTargetLowering::getRegForInlineAsmCon
> // GCC RS6000 Constraint Letters
> switch (Constraint[0]) {
> case 'b': // R1-R31
> + if (VT == MVT::i64 && PPCSubTarget.isPPC64())
> + return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
> + return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
> case 'r': // R0-R31
> if (VT == MVT::i64 && PPCSubTarget.isPPC64())
> return std::make_pair(0U, &PPC::G8RCRegClass);
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=177423&r1=177422&r2=177423&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Tue Mar 19
> 13:51:05 2013
> @@ -35,7 +35,7 @@ def tocentry : Operand<iPTR> {
> def memrs : Operand<iPTR> { // memri where the immediate is a
> symbolLo64
> let PrintMethod = "printMemRegImm";
> let EncoderMethod = "getMemRIXEncoding";
> - let MIOperandInfo = (ops symbolLo64:$off, ptr_rc:$reg);
> + let MIOperandInfo = (ops symbolLo64:$off, ptr_rc_nor0:$reg);
> }
> def tlsreg : Operand<i64> {
> let EncoderMethod = "getTLSRegEncoding";
> @@ -353,6 +353,15 @@ def XOR8 : XForm_6<31, 316, (outs G8RC:$
> "xor $rA, $rS, $rB", IntSimple,
> [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
>
> +// Moves between 32-bit and 64-bit registers (used for copy
> resolution
> +// after register allocation).
> +let isCodeGenOnly = 1 in {
> +def OR8_32 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS,
> GPRC:$rB),
> + "or $rA, $rS, $rB", IntSimple, []>;
> +def OR_64 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS,
> G8RC:$rB),
> + "or $rA, $rS, $rB", IntSimple, []>;
> +}
> +
> // Logical ops with immediate.
> def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1,
> u16imm:$src2),
> "andi. $dst, $src1, $src2", IntGeneral,
> @@ -393,15 +402,16 @@ def ADDIC8 : DForm_2<12, (outs G8RC:$rD)
> "addic $rD, $rA, $imm", IntGeneral,
> [(set G8RC:$rD, (addc G8RC:$rA,
> immSExt16:$imm))]>;
> }
> -def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA,
> s16imm64:$imm),
> +def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC_NOX0:$rA,
> s16imm64:$imm),
> "addi $rD, $rA, $imm", IntSimple,
> - [(set G8RC:$rD, (add G8RC:$rA,
> immSExt16:$imm))]>;
> -def ADDI8L : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA,
> symbolLo64:$imm),
> + [(set G8RC:$rD, (add G8RC_NOX0:$rA,
> immSExt16:$imm))]>;
> +def ADDI8L : DForm_2<14, (outs G8RC:$rD), (ins G8RC_NOX0:$rA,
> symbolLo64:$imm),
> "addi $rD, $rA, $imm", IntSimple,
> - [(set G8RC:$rD, (add G8RC:$rA,
> immSExt16:$imm))]>;
> -def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA,
> symbolHi64:$imm),
> + [(set G8RC:$rD, (add G8RC_NOX0:$rA,
> immSExt16:$imm))]>;
> +def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC_NOX0:$rA,
> symbolHi64:$imm),
> "addis $rD, $rA, $imm", IntSimple,
> - [(set G8RC:$rD, (add G8RC:$rA,
> imm16ShiftedSExt:$imm))]>;
> + [(set G8RC:$rD, (add G8RC_NOX0:$rA,
> + imm16ShiftedSExt:$imm))]>;
>
> let Defs = [CARRY] in {
> def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA,
> s16imm64:$imm),
> @@ -536,7 +546,7 @@ def RLWINM8 : MForm_2<21,
> []>;
>
> def ISEL8 : AForm_4<31, 15,
> - (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB,
> pred:$cond),
> + (outs G8RC:$rT), (ins G8RC_NOX0:$rA, G8RC:$rB,
> pred:$cond),
> "isel $rT, $rA, $rB, $cond", IntGeneral,
> []>;
> } // End FXU Operations.
> @@ -569,19 +579,19 @@ def LWAX : XForm_1<31, 341, (outs G8RC:$
>
> // Update forms.
> let mayLoad = 1 in
> -def LHAU8 : DForm_1a<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins
> symbolLo:$disp,
> - ptr_rc:$rA),
> +def LHAU8 : DForm_1a<43, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
> (ins symbolLo:$disp,
> + ptr_rc_nor0:$rA),
> "lhau $rD, $disp($rA)", LdStLHAU,
> []>, RegConstraint<"$rA = $ea_result">,
> NoEncode<"$ea_result">;
> // NO LWAU!
>
> -def LHAUX8 : XForm_1<31, 375, (outs G8RC:$rD, ptr_rc:$ea_result),
> +def LHAUX8 : XForm_1<31, 375, (outs G8RC:$rD,
> ptr_rc_nor0:$ea_result),
> (ins memrr:$addr),
> "lhaux $rD, $addr", LdStLHAU,
> []>, RegConstraint<"$addr.offreg = $ea_result">,
> NoEncode<"$ea_result">;
> -def LWAUX : XForm_1<31, 373, (outs G8RC:$rD, ptr_rc:$ea_result),
> +def LWAUX : XForm_1<31, 373, (outs G8RC:$rD,
> ptr_rc_nor0:$ea_result),
> (ins memrr:$addr),
> "lwaux $rD, $addr", LdStLHAU,
> []>, RegConstraint<"$addr.offreg = $ea_result">,
> @@ -613,30 +623,30 @@ def LWZX8 : XForm_1<31, 23, (outs G8RC:
>
> // Update forms.
> let mayLoad = 1 in {
> -def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins
> memri:$addr),
> +def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
> (ins memri:$addr),
> "lbzu $rD, $addr", LdStLoadUpd,
> []>, RegConstraint<"$addr.reg = $ea_result">,
> NoEncode<"$ea_result">;
> -def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins
> memri:$addr),
> +def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
> (ins memri:$addr),
> "lhzu $rD, $addr", LdStLoadUpd,
> []>, RegConstraint<"$addr.reg = $ea_result">,
> NoEncode<"$ea_result">;
> -def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins
> memri:$addr),
> +def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
> (ins memri:$addr),
> "lwzu $rD, $addr", LdStLoadUpd,
> []>, RegConstraint<"$addr.reg = $ea_result">,
> NoEncode<"$ea_result">;
>
> -def LBZUX8 : XForm_1<31, 119, (outs G8RC:$rD, ptr_rc:$ea_result),
> +def LBZUX8 : XForm_1<31, 119, (outs G8RC:$rD,
> ptr_rc_nor0:$ea_result),
> (ins memrr:$addr),
> "lbzux $rD, $addr", LdStLoadUpd,
> []>, RegConstraint<"$addr.offreg = $ea_result">,
> NoEncode<"$ea_result">;
> -def LHZUX8 : XForm_1<31, 311, (outs G8RC:$rD, ptr_rc:$ea_result),
> +def LHZUX8 : XForm_1<31, 311, (outs G8RC:$rD,
> ptr_rc_nor0:$ea_result),
> (ins memrr:$addr),
> "lhzux $rD, $addr", LdStLoadUpd,
> []>, RegConstraint<"$addr.offreg = $ea_result">,
> NoEncode<"$ea_result">;
> -def LWZUX8 : XForm_1<31, 55, (outs G8RC:$rD, ptr_rc:$ea_result),
> +def LWZUX8 : XForm_1<31, 55, (outs G8RC:$rD,
> ptr_rc_nor0:$ea_result),
> (ins memrr:$addr),
> "lwzux $rD, $addr", LdStLoadUpd,
> []>, RegConstraint<"$addr.offreg = $ea_result">,
> @@ -685,12 +695,12 @@ def LDX : XForm_1<31, 21, (outs G8RC:$
> [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
>
> let mayLoad = 1 in
> -def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins
> memrix:$addr),
> +def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
> (ins memrix:$addr),
> "ldu $rD, $addr", LdStLDU,
> []>, RegConstraint<"$addr.reg = $ea_result">,
> isPPC64,
> NoEncode<"$ea_result">;
>
> -def LDUX : XForm_1<31, 53, (outs G8RC:$rD, ptr_rc:$ea_result),
> +def LDUX : XForm_1<31, 53, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
> (ins memrr:$addr),
> "ldux $rD, $addr", LdStLDU,
> []>, RegConstraint<"$addr.offreg = $ea_result">,
> @@ -808,70 +818,70 @@ def STDX : XForm_8<31, 149, (outs), (in
>
> let PPC970_Unit = 2 in {
>
> -def STBU8 : DForm_1a<39, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
> - symbolLo:$ptroff, ptr_rc:$ptrreg),
> +def STBU8 : DForm_1a<39, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS,
> + symbolLo:$ptroff, ptr_rc_nor0:$ptrreg),
> "stbu $rS, $ptroff($ptrreg)", LdStStoreUpd,
> - [(set ptr_rc:$ea_res,
> - (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg,
> + [(set ptr_rc_nor0:$ea_res,
> + (pre_truncsti8 G8RC:$rS,
> ptr_rc_nor0:$ptrreg,
> iaddroff:$ptroff))]>,
> RegConstraint<"$ptrreg = $ea_res">,
> NoEncode<"$ea_res">;
> -def STHU8 : DForm_1a<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
> - symbolLo:$ptroff, ptr_rc:$ptrreg),
> +def STHU8 : DForm_1a<45, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS,
> + symbolLo:$ptroff, ptr_rc_nor0:$ptrreg),
> "sthu $rS, $ptroff($ptrreg)", LdStStoreUpd,
> - [(set ptr_rc:$ea_res,
> - (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg,
> + [(set ptr_rc_nor0:$ea_res,
> + (pre_truncsti16 G8RC:$rS,
> ptr_rc_nor0:$ptrreg,
> iaddroff:$ptroff))]>,
> RegConstraint<"$ptrreg = $ea_res">,
> NoEncode<"$ea_res">;
>
> -def STWU8 : DForm_1a<37, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
> - symbolLo:$ptroff, ptr_rc:$ptrreg),
> +def STWU8 : DForm_1a<37, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS,
> + symbolLo:$ptroff, ptr_rc_nor0:$ptrreg),
> "stwu $rS, $ptroff($ptrreg)", LdStStoreUpd,
> - [(set ptr_rc:$ea_res,
> - (pre_truncsti32 G8RC:$rS, ptr_rc:$ptrreg,
> + [(set ptr_rc_nor0:$ea_res,
> + (pre_truncsti32 G8RC:$rS,
> ptr_rc_nor0:$ptrreg,
> iaddroff:$ptroff))]>,
> RegConstraint<"$ptrreg = $ea_res">,
> NoEncode<"$ea_res">;
>
> -def STDU : DSForm_1a<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
> - s16immX4:$ptroff,
> ptr_rc:$ptrreg),
> +def STDU : DSForm_1a<62, 1, (outs ptr_rc_nor0:$ea_res), (ins
> G8RC:$rS,
> + s16immX4:$ptroff,
> ptr_rc_nor0:$ptrreg),
> "stdu $rS, $ptroff($ptrreg)", LdStSTDU,
> - [(set ptr_rc:$ea_res,
> - (aligned4pre_store G8RC:$rS, ptr_rc:$ptrreg,
> + [(set ptr_rc_nor0:$ea_res,
> + (aligned4pre_store G8RC:$rS,
> ptr_rc_nor0:$ptrreg,
> iaddroff:$ptroff))]>,
> RegConstraint<"$ptrreg = $ea_res">,
> NoEncode<"$ea_res">,
> isPPC64;
>
>
> -def STBUX8 : XForm_8<31, 247, (outs ptr_rc:$ea_res),
> - (ins G8RC:$rS, ptr_rc:$ptroff,
> ptr_rc:$ptrreg),
> +def STBUX8 : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res),
> + (ins G8RC:$rS, ptr_rc_nor0:$ptroff,
> ptr_rc:$ptrreg),
> "stbux $rS, $ptroff, $ptrreg", LdStStoreUpd,
> - [(set ptr_rc:$ea_res,
> + [(set ptr_rc_nor0:$ea_res,
> (pre_truncsti8 G8RC:$rS,
> ptr_rc:$ptrreg,
> xaddroff:$ptroff))]>,
> RegConstraint<"$ptroff = $ea_res">,
> NoEncode<"$ea_res">,
> PPC970_DGroup_Cracked;
>
> -def STHUX8 : XForm_8<31, 439, (outs ptr_rc:$ea_res),
> - (ins G8RC:$rS, ptr_rc:$ptroff,
> ptr_rc:$ptrreg),
> +def STHUX8 : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res),
> + (ins G8RC:$rS, ptr_rc_nor0:$ptroff,
> ptr_rc:$ptrreg),
> "sthux $rS, $ptroff, $ptrreg", LdStStoreUpd,
> - [(set ptr_rc:$ea_res,
> + [(set ptr_rc_nor0:$ea_res,
> (pre_truncsti16 G8RC:$rS,
> ptr_rc:$ptrreg,
> xaddroff:$ptroff))]>,
> RegConstraint<"$ptroff = $ea_res">,
> NoEncode<"$ea_res">,
> PPC970_DGroup_Cracked;
>
> -def STWUX8 : XForm_8<31, 183, (outs ptr_rc:$ea_res),
> - (ins G8RC:$rS, ptr_rc:$ptroff,
> ptr_rc:$ptrreg),
> +def STWUX8 : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res),
> + (ins G8RC:$rS, ptr_rc_nor0:$ptroff,
> ptr_rc:$ptrreg),
> "stwux $rS, $ptroff, $ptrreg", LdStStoreUpd,
> - [(set ptr_rc:$ea_res,
> + [(set ptr_rc_nor0:$ea_res,
> (pre_truncsti32 G8RC:$rS,
> ptr_rc:$ptrreg,
> xaddroff:$ptroff))]>,
> RegConstraint<"$ptroff = $ea_res">,
> NoEncode<"$ea_res">,
> PPC970_DGroup_Cracked;
>
> -def STDUX : XForm_8<31, 181, (outs ptr_rc:$ea_res),
> - (ins G8RC:$rS, ptr_rc:$ptroff,
> ptr_rc:$ptrreg),
> +def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res),
> + (ins G8RC:$rS, ptr_rc_nor0:$ptroff,
> ptr_rc:$ptrreg),
> "stdux $rS, $ptroff, $ptrreg", LdStSTDU,
> - [(set ptr_rc:$ea_res,
> + [(set ptr_rc_nor0:$ea_res,
> (pre_store G8RC:$rS, ptr_rc:$ptrreg,
> xaddroff:$ptroff))]>,
> RegConstraint<"$ptroff = $ea_res">,
> NoEncode<"$ea_res">,
> PPC970_DGroup_Cracked, isPPC64;
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=177423&r1=177422&r2=177423&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Tue Mar 19
> 13:51:05 2013
> @@ -422,6 +422,15 @@ void PPCInstrInfo::copyPhysReg(MachineBa
> Opc = PPC::VOR;
> else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
> Opc = PPC::CROR;
> +
> + // Asymmetric copies:
> +
> + else if (PPC::GPRCRegClass.contains(DestReg) &&
> + PPC::G8RCRegClass.contains(SrcReg))
> + Opc = PPC::OR_64;
> + else if (PPC::G8RCRegClass.contains(DestReg) &&
> + PPC::GPRCRegClass.contains(SrcReg))
> + Opc = PPC::OR8_32;
> else
> llvm_unreachable("Impossible reg-to-reg copy");
>
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=177423&r1=177422&r2=177423&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Tue Mar 19 13:51:05
> 2013
> @@ -376,18 +376,21 @@ def crbitm: Operand<i8> {
> let EncoderMethod = "get_crbitm_encoding";
> }
> // Address operands
> +// A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
> +def ptr_rc_nor0 : PointerLikeRegClass<1>;
> +
> def memri : Operand<iPTR> {
> let PrintMethod = "printMemRegImm";
> - let MIOperandInfo = (ops symbolLo:$imm, ptr_rc:$reg);
> + let MIOperandInfo = (ops symbolLo:$imm, ptr_rc_nor0:$reg);
> let EncoderMethod = "getMemRIEncoding";
> }
> def memrr : Operand<iPTR> {
> let PrintMethod = "printMemRegReg";
> - let MIOperandInfo = (ops ptr_rc:$offreg, ptr_rc:$ptrreg);
> + let MIOperandInfo = (ops ptr_rc_nor0:$offreg, ptr_rc:$ptrreg);
> }
> def memrix : Operand<iPTR> { // memri where the imm is shifted 2
> bits.
> let PrintMethod = "printMemRegImmShifted";
> - let MIOperandInfo = (ops symbolLo:$imm, ptr_rc:$reg);
> + let MIOperandInfo = (ops symbolLo:$imm, ptr_rc_nor0:$reg);
> let EncoderMethod = "getMemRIXEncoding";
> }
>
> @@ -740,69 +743,69 @@ def LFD : DForm_1<50, (outs F8RC:$rD), (
>
> // Unindexed (r+i) Loads with Update (preinc).
> let mayLoad = 1 in {
> -def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins
> memri:$addr),
> +def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins
> memri:$addr),
> "lbzu $rD, $addr", LdStLoadUpd,
> []>, RegConstraint<"$addr.reg = $ea_result">,
> NoEncode<"$ea_result">;
>
> -def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins
> memri:$addr),
> +def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins
> memri:$addr),
> "lhau $rD, $addr", LdStLHAU,
> []>, RegConstraint<"$addr.reg = $ea_result">,
> NoEncode<"$ea_result">;
>
> -def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins
> memri:$addr),
> +def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins
> memri:$addr),
> "lhzu $rD, $addr", LdStLoadUpd,
> []>, RegConstraint<"$addr.reg = $ea_result">,
> NoEncode<"$ea_result">;
>
> -def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins
> memri:$addr),
> +def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins
> memri:$addr),
> "lwzu $rD, $addr", LdStLoadUpd,
> []>, RegConstraint<"$addr.reg = $ea_result">,
> NoEncode<"$ea_result">;
>
> -def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins
> memri:$addr),
> +def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc_nor0:$ea_result), (ins
> memri:$addr),
> "lfsu $rD, $addr", LdStLFDU,
> []>, RegConstraint<"$addr.reg = $ea_result">,
> NoEncode<"$ea_result">;
>
> -def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins
> memri:$addr),
> +def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc_nor0:$ea_result), (ins
> memri:$addr),
> "lfdu $rD, $addr", LdStLFDU,
> []>, RegConstraint<"$addr.reg = $ea_result">,
> NoEncode<"$ea_result">;
>
>
> // Indexed (r+r) Loads with Update (preinc).
> -def LBZUX : XForm_1<31, 119, (outs GPRC:$rD, ptr_rc:$ea_result),
> +def LBZUX : XForm_1<31, 119, (outs GPRC:$rD,
> ptr_rc_nor0:$ea_result),
> (ins memrr:$addr),
> "lbzux $rD, $addr", LdStLoadUpd,
> []>, RegConstraint<"$addr.offreg = $ea_result">,
> NoEncode<"$ea_result">;
>
> -def LHAUX : XForm_1<31, 375, (outs GPRC:$rD, ptr_rc:$ea_result),
> +def LHAUX : XForm_1<31, 375, (outs GPRC:$rD,
> ptr_rc_nor0:$ea_result),
> (ins memrr:$addr),
> "lhaux $rD, $addr", LdStLHAU,
> []>, RegConstraint<"$addr.offreg = $ea_result">,
> NoEncode<"$ea_result">;
>
> -def LHZUX : XForm_1<31, 311, (outs GPRC:$rD, ptr_rc:$ea_result),
> +def LHZUX : XForm_1<31, 311, (outs GPRC:$rD,
> ptr_rc_nor0:$ea_result),
> (ins memrr:$addr),
> "lhzux $rD, $addr", LdStLoadUpd,
> []>, RegConstraint<"$addr.offreg = $ea_result">,
> NoEncode<"$ea_result">;
>
> -def LWZUX : XForm_1<31, 55, (outs GPRC:$rD, ptr_rc:$ea_result),
> +def LWZUX : XForm_1<31, 55, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
> (ins memrr:$addr),
> "lwzux $rD, $addr", LdStLoadUpd,
> []>, RegConstraint<"$addr.offreg = $ea_result">,
> NoEncode<"$ea_result">;
>
> -def LFSUX : XForm_1<31, 567, (outs F4RC:$rD, ptr_rc:$ea_result),
> +def LFSUX : XForm_1<31, 567, (outs F4RC:$rD,
> ptr_rc_nor0:$ea_result),
> (ins memrr:$addr),
> "lfsux $rD, $addr", LdStLFDU,
> []>, RegConstraint<"$addr.offreg = $ea_result">,
> NoEncode<"$ea_result">;
>
> -def LFDUX : XForm_1<31, 631, (outs F8RC:$rD, ptr_rc:$ea_result),
> +def LFDUX : XForm_1<31, 631, (outs F8RC:$rD,
> ptr_rc_nor0:$ea_result),
> (ins memrr:$addr),
> "lfdux $rD, $addr", LdStLFDU,
> []>, RegConstraint<"$addr.offreg = $ea_result">,
> @@ -868,36 +871,36 @@ def STFD : DForm_1<54, (outs), (ins F8RC
>
> // Unindexed (r+i) Stores with Update (preinc).
> let PPC970_Unit = 2 in {
> -def STBU : DForm_1a<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
> - symbolLo:$ptroff, ptr_rc:$ptrreg),
> +def STBU : DForm_1a<39, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS,
> + symbolLo:$ptroff, ptr_rc_nor0:$ptrreg),
> "stbu $rS, $ptroff($ptrreg)", LdStStoreUpd,
> - [(set ptr_rc:$ea_res,
> - (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
> + [(set ptr_rc_nor0:$ea_res,
> + (pre_truncsti8 GPRC:$rS,
> ptr_rc_nor0:$ptrreg,
> iaddroff:$ptroff))]>,
> RegConstraint<"$ptrreg = $ea_res">,
> NoEncode<"$ea_res">;
> -def STHU : DForm_1a<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
> - symbolLo:$ptroff, ptr_rc:$ptrreg),
> +def STHU : DForm_1a<45, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS,
> + symbolLo:$ptroff, ptr_rc_nor0:$ptrreg),
> "sthu $rS, $ptroff($ptrreg)", LdStStoreUpd,
> - [(set ptr_rc:$ea_res,
> - (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
> + [(set ptr_rc_nor0:$ea_res,
> + (pre_truncsti16 GPRC:$rS,
> ptr_rc_nor0:$ptrreg,
> iaddroff:$ptroff))]>,
> RegConstraint<"$ptrreg = $ea_res">,
> NoEncode<"$ea_res">;
> -def STWU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
> - symbolLo:$ptroff, ptr_rc:$ptrreg),
> +def STWU : DForm_1a<37, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS,
> + symbolLo:$ptroff, ptr_rc_nor0:$ptrreg),
> "stwu $rS, $ptroff($ptrreg)", LdStStoreUpd,
> - [(set ptr_rc:$ea_res, (pre_store GPRC:$rS,
> ptr_rc:$ptrreg,
> + [(set ptr_rc_nor0:$ea_res, (pre_store GPRC:$rS,
> ptr_rc_nor0:$ptrreg,
> iaddroff:$ptroff))]>,
> RegConstraint<"$ptrreg = $ea_res">,
> NoEncode<"$ea_res">;
> -def STFSU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
> - symbolLo:$ptroff, ptr_rc:$ptrreg),
> +def STFSU : DForm_1a<37, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS,
> + symbolLo:$ptroff, ptr_rc_nor0:$ptrreg),
> "stfsu $rS, $ptroff($ptrreg)", LdStSTFDU,
> - [(set ptr_rc:$ea_res, (pre_store F4RC:$rS,
> ptr_rc:$ptrreg,
> + [(set ptr_rc_nor0:$ea_res, (pre_store F4RC:$rS,
> ptr_rc_nor0:$ptrreg,
> iaddroff:$ptroff))]>,
> RegConstraint<"$ptrreg = $ea_res">,
> NoEncode<"$ea_res">;
> -def STFDU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
> - symbolLo:$ptroff, ptr_rc:$ptrreg),
> +def STFDU : DForm_1a<37, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS,
> + symbolLo:$ptroff, ptr_rc_nor0:$ptrreg),
> "stfdu $rS, $ptroff($ptrreg)", LdStSTFDU,
> - [(set ptr_rc:$ea_res, (pre_store F8RC:$rS,
> ptr_rc:$ptrreg,
> + [(set ptr_rc_nor0:$ea_res, (pre_store F8RC:$rS,
> ptr_rc_nor0:$ptrreg,
> iaddroff:$ptroff))]>,
> RegConstraint<"$ptrreg = $ea_res">,
> NoEncode<"$ea_res">;
> }
> @@ -919,44 +922,44 @@ def STWX : XForm_8<31, 151, (outs), (in
> [(store GPRC:$rS, xaddr:$dst)]>,
> PPC970_DGroup_Cracked;
>
> -def STBUX : XForm_8<31, 247, (outs ptr_rc:$ea_res),
> - (ins GPRC:$rS, ptr_rc:$ptroff,
> ptr_rc:$ptrreg),
> +def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res),
> + (ins GPRC:$rS, ptr_rc_nor0:$ptroff,
> ptr_rc:$ptrreg),
> "stbux $rS, $ptroff, $ptrreg", LdStStoreUpd,
> - [(set ptr_rc:$ea_res,
> + [(set ptr_rc_nor0:$ea_res,
> (pre_truncsti8 GPRC:$rS,
> ptr_rc:$ptrreg,
> xaddroff:$ptroff))]>,
> RegConstraint<"$ptroff = $ea_res">,
> NoEncode<"$ea_res">,
> PPC970_DGroup_Cracked;
>
> -def STHUX : XForm_8<31, 439, (outs ptr_rc:$ea_res),
> - (ins GPRC:$rS, ptr_rc:$ptroff,
> ptr_rc:$ptrreg),
> +def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res),
> + (ins GPRC:$rS, ptr_rc_nor0:$ptroff,
> ptr_rc:$ptrreg),
> "sthux $rS, $ptroff, $ptrreg", LdStStoreUpd,
> - [(set ptr_rc:$ea_res,
> + [(set ptr_rc_nor0:$ea_res,
> (pre_truncsti16 GPRC:$rS,
> ptr_rc:$ptrreg,
> xaddroff:$ptroff))]>,
> RegConstraint<"$ptroff = $ea_res">,
> NoEncode<"$ea_res">,
> PPC970_DGroup_Cracked;
>
> -def STWUX : XForm_8<31, 183, (outs ptr_rc:$ea_res),
> - (ins GPRC:$rS, ptr_rc:$ptroff,
> ptr_rc:$ptrreg),
> +def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res),
> + (ins GPRC:$rS, ptr_rc_nor0:$ptroff,
> ptr_rc:$ptrreg),
> "stwux $rS, $ptroff, $ptrreg", LdStStoreUpd,
> - [(set ptr_rc:$ea_res,
> + [(set ptr_rc_nor0:$ea_res,
> (pre_store GPRC:$rS, ptr_rc:$ptrreg,
> xaddroff:$ptroff))]>,
> RegConstraint<"$ptroff = $ea_res">,
> NoEncode<"$ea_res">,
> PPC970_DGroup_Cracked;
>
> -def STFSUX : XForm_8<31, 695, (outs ptr_rc:$ea_res),
> - (ins F4RC:$rS, ptr_rc:$ptroff,
> ptr_rc:$ptrreg),
> +def STFSUX : XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res),
> + (ins F4RC:$rS, ptr_rc_nor0:$ptroff,
> ptr_rc:$ptrreg),
> "stfsux $rS, $ptroff, $ptrreg", LdStSTFDU,
> - [(set ptr_rc:$ea_res,
> + [(set ptr_rc_nor0:$ea_res,
> (pre_store F4RC:$rS, ptr_rc:$ptrreg,
> xaddroff:$ptroff))]>,
> RegConstraint<"$ptroff = $ea_res">,
> NoEncode<"$ea_res">,
> PPC970_DGroup_Cracked;
>
> -def STFDUX : XForm_8<31, 759, (outs ptr_rc:$ea_res),
> - (ins F8RC:$rS, ptr_rc:$ptroff,
> ptr_rc:$ptrreg),
> +def STFDUX : XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res),
> + (ins F8RC:$rS, ptr_rc_nor0:$ptroff,
> ptr_rc:$ptrreg),
> "stfdux $rS, $ptroff, $ptrreg", LdStSTFDU,
> - [(set ptr_rc:$ea_res,
> + [(set ptr_rc_nor0:$ea_res,
> (pre_store F8RC:$rS, ptr_rc:$ptrreg,
> xaddroff:$ptroff))]>,
> RegConstraint<"$ptroff = $ea_res">,
> NoEncode<"$ea_res">,
> PPC970_DGroup_Cracked;
> @@ -991,12 +994,12 @@ def SYNC : XForm_24_sync<31, 598, (outs)
> //
>
> let PPC970_Unit = 1 in { // FXU Operations.
> -def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA,
> s16imm:$imm),
> +def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA,
> s16imm:$imm),
> "addi $rD, $rA, $imm", IntSimple,
> - [(set GPRC:$rD, (add GPRC:$rA,
> immSExt16:$imm))]>;
> -def ADDIL : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA,
> symbolLo:$imm),
> + [(set GPRC:$rD, (add GPRC_NOR0:$rA,
> immSExt16:$imm))]>;
> +def ADDIL : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA,
> symbolLo:$imm),
> "addi $rD, $rA, $imm", IntSimple,
> - [(set GPRC:$rD, (add GPRC:$rA,
> immSExt16:$imm))]>;
> + [(set GPRC:$rD, (add GPRC_NOR0:$rA,
> immSExt16:$imm))]>;
> let Defs = [CARRY] in {
> def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA,
> s16imm:$imm),
> "addic $rD, $rA, $imm", IntGeneral,
> @@ -1006,12 +1009,13 @@ def ADDICo : DForm_2<13, (outs GPRC:$rD)
> "addic. $rD, $rA, $imm", IntGeneral,
> []>;
> }
> -def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA,
> symbolHi:$imm),
> +def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC_NOR0:$rA,
> symbolHi:$imm),
> "addis $rD, $rA, $imm", IntSimple,
> - [(set GPRC:$rD, (add GPRC:$rA,
> imm16ShiftedSExt:$imm))]>;
> -def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA,
> symbolLo:$sym),
> + [(set GPRC:$rD, (add GPRC_NOR0:$rA,
> + imm16ShiftedSExt:$imm))]>;
> +def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA,
> symbolLo:$sym),
> "la $rD, $sym($rA)", IntGeneral,
> - [(set GPRC:$rD, (add GPRC:$rA,
> + [(set GPRC:$rD, (add GPRC_NOR0:$rA,
> (PPClo tglobaladdr:$sym,
> 0)))]>;
> def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA,
> s16imm:$imm),
> "mulli $rD, $rA, $imm", IntMulLI,
> @@ -1467,7 +1471,7 @@ let Uses = [RM] in {
>
> let PPC970_Unit = 1 in { // FXU Operations.
> def ISEL : AForm_4<31, 15,
> - (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB,
> pred:$cond),
> + (outs GPRC:$rT), (ins GPRC_NOR0:$rA, GPRC:$rB,
> pred:$cond),
> "isel $rT, $rA, $rB, $cond", IntGeneral,
> []>;
> }
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=177423&r1=177422&r2=177423&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Mar 19
> 13:51:05 2013
> @@ -76,6 +76,12 @@ PPCRegisterInfo::PPCRegisterInfo(const P
> const TargetRegisterClass *
> PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF,
> unsigned Kind)
> const
> {
> + if (Kind == 1) {
> + if (Subtarget.isPPC64())
> + return &PPC::G8RC_NOX0RegClass;
> + return &PPC::GPRC_NOR0RegClass;
> + }
> +
> if (Subtarget.isPPC64())
> return &PPC::G8RCRegClass;
> return &PPC::GPRCRegClass;
> @@ -104,6 +110,10 @@ BitVector PPCRegisterInfo::getReservedRe
> const PPCFrameLowering *PPCFI =
> static_cast<const
> PPCFrameLowering*>(MF.getTarget().getFrameLowering());
>
> + // The ZERO register is not really a register, but the
> representation of r0
> + // when used in instructions that treat r0 as the constant 0.
> + Reserved.set(PPC::ZERO);
> +
> Reserved.set(PPC::R0);
> Reserved.set(PPC::R1);
> Reserved.set(PPC::LR);
> @@ -148,6 +158,8 @@ PPCRegisterInfo::getRegPressureLimit(con
> switch (RC->getID()) {
> default:
> return 0;
> + case PPC::G8RC_NOX0RegClassID:
> + case PPC::GPRC_NOR0RegClassID:
> case PPC::G8RCRegClassID:
> case PPC::GPRCRegClassID: {
> unsigned FP = TFI->hasFP(MF) ? 1 : 0;
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td?rev=177423&r1=177422&r2=177423&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td Tue Mar 19
> 13:51:05 2013
> @@ -86,6 +86,9 @@ foreach Index = 0-31 in {
> DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>;
> }
>
> +// The reprsentation of r0 when treated as the constant 0.
> +def ZERO : GPR<0, "r0">;
> +
> // Condition register bits
> def CR0LT : CRBIT< 0, "0">;
> def CR0GT : CRBIT< 1, "1">;
> @@ -170,6 +173,12 @@ def G8RC : RegisterClass<"PPC", [i64], 6
> (sequence "X%u", 30,
> 14),
> X31, X13, X0, X1,
> LR8)>;
>
> +// For some instructions r0 is special (representing the value 0
> instead of
> +// the value in the r0 register), and we use these register
> subclasses to
> +// prevent r0 from being allocated for use by those instructions.
> +def GPRC_NOR0 : RegisterClass<"PPC", [i32], 32, (add (sub GPRC, R0),
> ZERO)>;
> +def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0),
> ZERO)>;
> +
> // Allocate volatiles first, then non-volatiles in reverse order.
> With the SVR4
> // ABI the size of the Floating-point register save area is
> determined by the
> // allocated non-volatile register with the lowest register number,
> as FP
>
> Added: llvm/trunk/test/CodeGen/PowerPC/asym-regclass-copy.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/asym-regclass-copy.ll?rev=177423&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/asym-regclass-copy.ll (added)
> +++ llvm/trunk/test/CodeGen/PowerPC/asym-regclass-copy.ll Tue Mar 19
> 13:51:05 2013
> @@ -0,0 +1,53 @@
> +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7
> +target datalayout =
> "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
> +target triple = "powerpc64-unknown-linux-gnu"
> +
> + at gen_random.last = external unnamed_addr global i64, align 8
> + at .str = external unnamed_addr constant [4 x i8], align 1
> +
> +declare double @gen_random(double) #0
> +
> +declare void @benchmark_heapsort(i32 signext, double* nocapture) #0
> +
> +define signext i32 @main(i32 signext %argc, i8** nocapture %argv) #0
> {
> +entry:
> + br i1 undef, label %cond.true, label %cond.end
> +
> +cond.true: ; preds = %entry
> + br label %cond.end
> +
> +cond.end: ; preds =
> %cond.true, %entry
> + %cond = phi i32 [ 0, %cond.true ], [ 8000000, %entry ]
> + %add = add i32 %cond, 1
> + %conv = sext i32 %add to i64
> + %mul = shl nsw i64 %conv, 3
> + %call1 = tail call noalias i8* @malloc(i64 %mul) #1
> + br i1 undef, label %for.end, label %for.body.lr.ph
> +
> +for.body.lr.ph: ; preds =
> %cond.end
> + br label %for.body
> +
> +for.body: ; preds =
> %for.body, %for.body.lr.ph
> + %indvars.iv = phi i64 [ 1, %for.body.lr.ph ], [ %indvars.iv.next,
> %for.body ]
> + %indvars.iv.next = add i64 %indvars.iv, 1
> + %lftr.wideiv = trunc i64 %indvars.iv.next to i32
> + %exitcond = icmp eq i32 %lftr.wideiv, %add
> + br i1 %exitcond, label %for.cond.for.end_crit_edge, label
> %for.body
> +
> +for.cond.for.end_crit_edge: ; preds =
> %for.body
> + br label %for.end
> +
> +for.end: ; preds =
> %for.cond.for.end_crit_edge, %cond.end
> + ret i32 0
> +}
> +
> +declare noalias i8* @malloc(i64) #0
> +
> +declare signext i32 @printf(i8* nocapture, ...) #0
> +
> +declare void @free(i8* nocapture) #0
> +
> +declare i64 @strtol(i8*, i8** nocapture, i32 signext) #0
> +
> +attributes #0 = { nounwind "less-precise-fpmad"="false"
> "no-frame-pointer-elim"="false"
> "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false"
> "no-nans-fp-math"="false" "unsafe-fp-math"="false"
> "use-soft-float"="false" }
> +attributes #1 = { nounwind }
>
>
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