[llvm] r177199 - Add SchedRW as an Instruction field.

[Jakob Stoklund Olesen]

Author: stoklund
Date: Fri Mar 15 17:51:13 2013
New Revision: 177199

URL: http://llvm.org/viewvc/llvm-project?rev=177199&view=rev
Log:
Add SchedRW as an Instruction field.

Don't require instructions to inherit Sched<...>. Sometimes it is more
convenient to say:

  let SchedRW = ... in {
    ...
  }

Which is now possible.

Modified:
    llvm/trunk/include/llvm/TableGen/Record.h
    llvm/trunk/include/llvm/Target/Target.td
    llvm/trunk/utils/TableGen/CodeGenSchedule.cpp

Modified: llvm/trunk/include/llvm/TableGen/Record.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/TableGen/Record.h?rev=177199&r1=177198&r2=177199&view=diff
==============================================================================
--- llvm/trunk/include/llvm/TableGen/Record.h (original)
+++ llvm/trunk/include/llvm/TableGen/Record.h Fri Mar 15 17:51:13 2013
@@ -1559,6 +1559,11 @@ public:
   ///
   Init *getValueInit(StringRef FieldName) const;
 
+  /// Return true if the named field is unset.
+  bool isValueUnset(StringRef FieldName) const {
+    return getValueInit(FieldName) == UnsetInit::get();
+  }
+
   /// getValueAsString - This method looks up the specified field and returns
   /// its value as a string, throwing an exception if the field does not exist
   /// or if the value is not a string.

Modified: llvm/trunk/include/llvm/Target/Target.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=177199&r1=177198&r2=177199&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/Target.td (original)
+++ llvm/trunk/include/llvm/Target/Target.td Fri Mar 15 17:51:13 2013
@@ -397,6 +397,9 @@ class Instruction {
 
   InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
 
+  // Scheduling information from TargetSchedule.td.
+  list<SchedReadWrite> SchedRW;
+
   string Constraints = "";  // OperandConstraint, e.g. $src = $dst.
 
   /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not

Modified: llvm/trunk/utils/TableGen/CodeGenSchedule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenSchedule.cpp?rev=177199&r1=177198&r2=177199&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenSchedule.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenSchedule.cpp Fri Mar 15 17:51:13 2013
@@ -217,7 +217,7 @@ void CodeGenSchedModels::collectSchedRW(
   for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
          E = Target.inst_end(); I != E; ++I) {
     Record *SchedDef = (*I)->TheDef;
-    if (!SchedDef->isSubClassOf("Sched"))
+    if (SchedDef->isValueUnset("SchedRW"))
       continue;
     RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW");
     for (RecIter RWI = RWs.begin(), RWE = RWs.end(); RWI != RWE; ++RWI) {
@@ -529,7 +529,7 @@ void CodeGenSchedModels::collectSchedCla
   // instruction definition that inherits from class Sched.
   for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
          E = Target.inst_end(); I != E; ++I) {
-    if (!(*I)->TheDef->isSubClassOf("Sched"))
+    if ((*I)->TheDef->isValueUnset("SchedRW"))
       continue;
     IdxVec Writes, Reads;
     findRWs((*I)->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
@@ -553,7 +553,7 @@ void CodeGenSchedModels::collectSchedCla
          E = Target.inst_end(); I != E; ++I) {
     Record *SchedDef = (*I)->TheDef;
     std::string InstName = (*I)->TheDef->getName();
-    if (SchedDef->isSubClassOf("Sched")) {
+    if (!SchedDef->isValueUnset("SchedRW")) {
       IdxVec Writes;
       IdxVec Reads;
       findRWs((*I)->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
@@ -584,7 +584,7 @@ void CodeGenSchedModels::collectSchedCla
       }
       continue;
     }
-    if (!SchedDef->isSubClassOf("Sched")
+    if (SchedDef->isValueUnset("SchedRW")
         && (SchedDef->getValueAsDef("Itinerary")->getName() == "NoItinerary")) {
       dbgs() << "No machine model for " << (*I)->TheDef->getName() << '\n';
     }
@@ -627,7 +627,7 @@ unsigned CodeGenSchedModels::getSchedCla
 
   // If this opcode isn't mapped by the subtarget fallback to the instruction
   // definition's SchedRW or ItinDef values.
-  if (Inst.TheDef->isSubClassOf("Sched")) {
+  if (!Inst.TheDef->isValueUnset("SchedRW")) {
     RecVec RWs = Inst.TheDef->getValueAsListOfDefs("SchedRW");
     return getSchedClassIdx(RWs);
   }
@@ -719,7 +719,7 @@ void CodeGenSchedModels::createInstRWCla
       // class because that is the fall-back class for other processors.
       Record *ItinDef = (*I)->getValueAsDef("Itinerary");
       SCIdx = SchedClassIdxMap.lookup(ItinDef->getName());
-      if (!SCIdx && (*I)->isSubClassOf("Sched"))
+      if (!SCIdx && !(*I)->isValueUnset("SchedRW"))
         SCIdx = getSchedClassIdx((*I)->getValueAsListOfDefs("SchedRW"));
     }
     unsigned CIdx = 0, CEnd = ClassInstrs.size();