[llvm-commits] [llvm] r171420 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll test/CodeGen/R600/vec4-expand.ll test/CodeGen/X86/cvtv2f32.ll
Michael Liao
michael.liao at intel.com
Wed Mar 13 22:24:48 PDT 2013
Hi Tom
The attached patch turned on the disabled test. xINT_TO_FP needs
checking both operand and result type and conversion is different from
regular ops. During type legalization, if result of conversion is
illegal, targets may ask to customize that. The previous logic needs
check only result type and need fixing to consider the operand as well.
R600 is not broken after this patch.
Yours
- Michael
On Wed, 2013-01-02 at 22:13 +0000, Tom Stellard wrote:
> Author: tstellar
> Date: Wed Jan 2 16:13:01 2013
> New Revision: 171420
>
> URL: http://llvm.org/viewvc/llvm-project?rev=171420&view=rev
> Log:
> DAGCombiner: Avoid generating illegal vector INT_TO_FP nodes
>
> DAGCombiner::reduceBuildVecConvertToConvertBuildVec() was making two
> mistakes:
>
> 1. It was checking the legality of scalar INT_TO_FP nodes and then generating
> vector nodes.
>
> 2. It was passing the result value type to
> TargetLoweringInfo::getOperationAction() when it should have been
> passing the value type of the first operand.
>
> Added:
> llvm/trunk/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll
> Modified:
> llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> llvm/trunk/test/CodeGen/R600/vec4-expand.ll
> llvm/trunk/test/CodeGen/X86/cvtv2f32.ll
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=171420&r1=171419&r2=171420&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Jan 2 16:13:01 2013
> @@ -8625,11 +8625,8 @@
> if (Opcode == ISD::DELETED_NODE &&
> (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) {
> Opcode = Opc;
> - // If not supported by target, bail out.
> - if (TLI.getOperationAction(Opcode, VT) != TargetLowering::Legal &&
> - TLI.getOperationAction(Opcode, VT) != TargetLowering::Custom)
> - return SDValue();
> }
> +
> if (Opc != Opcode)
> return SDValue();
>
> @@ -8654,6 +8651,10 @@
> assert(SrcVT != MVT::Other && "Cannot determine source type!");
>
> EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars);
> +
> + if (!TLI.isOperationLegalOrCustom(Opcode, NVT))
> + return SDValue();
> +
> SmallVector<SDValue, 8> Opnds;
> for (unsigned i = 0; i != NumInScalars; ++i) {
> SDValue In = N->getOperand(i);
>
> Added: llvm/trunk/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll?rev=171420&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll (added)
> +++ llvm/trunk/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll Wed Jan 2 16:13:01 2013
> @@ -0,0 +1,33 @@
> +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
> +
> +;CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +
> +; This test is for a bug in
> +; DAGCombiner::reduceBuildVecConvertToConvertBuildVec() where
> +; the wrong type was being passed to
> +; TargetLowering::getOperationAction() when checking the legality of
> +; ISD::UINT_TO_FP and ISD::SINT_TO_FP opcodes.
> +
> +define void @sint(<4 x float> addrspace(1)* %out, i32 addrspace(1)* %in) {
> +entry:
> + %ptr = getelementptr i32 addrspace(1)* %in, i32 1
> + %sint = load i32 addrspace(1) * %in
> + %conv = sitofp i32 %sint to float
> + %0 = insertelement <4 x float> undef, float %conv, i32 0
> + %splat = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer
> + store <4 x float> %splat, <4 x float> addrspace(1)* %out
> + ret void
> +}
> +
> +;CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
> +
> +define void @uint(<4 x float> addrspace(1)* %out, i32 addrspace(1)* %in) {
> +entry:
> + %ptr = getelementptr i32 addrspace(1)* %in, i32 1
> + %uint = load i32 addrspace(1) * %in
> + %conv = uitofp i32 %uint to float
> + %0 = insertelement <4 x float> undef, float %conv, i32 0
> + %splat = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer
> + store <4 x float> %splat, <4 x float> addrspace(1)* %out
> + ret void
> +}
>
> Modified: llvm/trunk/test/CodeGen/R600/vec4-expand.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/vec4-expand.ll?rev=171420&r1=171419&r2=171420&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/R600/vec4-expand.ll (original)
> +++ llvm/trunk/test/CodeGen/R600/vec4-expand.ll Wed Jan 2 16:13:01 2013
> @@ -1,6 +1,3 @@
> -; There are bugs in the DAGCombiner that prevent this test from passing.
> -; XFAIL: *
> -
> ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
>
> ; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
>
> Modified: llvm/trunk/test/CodeGen/X86/cvtv2f32.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cvtv2f32.ll?rev=171420&r1=171419&r2=171420&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/cvtv2f32.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/cvtv2f32.ll Wed Jan 2 16:13:01 2013
> @@ -1,3 +1,7 @@
> +; A bug fix in the DAGCombiner made this test fail, so marking as xfail
> +; until this can be investigated further.
> +; XFAIL: *
> +
> ; RUN: llc < %s -mtriple=i686-linux-pc -mcpu=corei7 | FileCheck %s
>
> define <2 x float> @foo(i32 %x, i32 %y, <2 x float> %v) {
>
>
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