[PATCH] Improve performance of vector code on A15

[Silviu Baranga]

Hi Jakob,

Probably with some careful use of VDUPLN(which would involve
mostly selecting the best lane to insert the SPR into) the VDUPfdf
pseudo could be replaced without anyone noticing. It's probably
worth removing since it's a potential source for some very nasty
bugs.

I removed the VDUPfdf pseudo usage from the patch to make it easier
for anyone that is trying to fully remove the pseudo inst. I did notice
some extra copies being inserted if the source lane was poorly chosen
(always inserting the SPR in lane 0 before doing the VDUP). So it looks
like the register coalescer won't do all the work.
After doing some minor adjustments these went away, so it's not that bad.

I also sorted out the MachineInstr insertion call. What confused me was
the fact that the following statement is true:
  MBB.end()->getParent() != MBB
which led me to the false conclusion that inserting at the end of the
basic block was not supported when in fact the arguments were wrong.

I'm attaching the new patch.

- Silviu

> -----Original Message-----
> From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk]
> Sent: 11 March 2013 18:42
> To: Silviu Baranga
> Cc: Tim Northover; James Molloy; Commit Messages and Patches for LLVM
> Subject: Re: [PATCH] Improve performance of vector code on A15
> 
> 
> On Mar 11, 2013, at 10:50 AM, Silviu Baranga <Silviu.Baranga at arm.com>
> wrote:
> 
> > I've also found a problem with the VDUPfdf/VUPfqf expansion which
> caused
> > the tests to not pass when adding -verify-machineinstrs. I'm
> attaching
> > a patch that should fix this. It has no test case since the test in
> the
> > other patch already relies on this change.
> 
> The register coalescer has improved a lot since these two pseudo-
> instructions were added. I wonder if they could be removed now?
> 
> IIRC, James already did something along those lines for NEONvduplane by
> using EXTRACT_SUBREG.
> 
> /jakob
> 
> 
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