SplitRes_SELECT improvement

[Duncan Sands]

Hi Richard,

On 12/03/13 17:55, Relph, Richard wrote:
>
> On Mar 12, 2013, at 9:30 AM, Nadav Rotem <nrotem at apple.com
> <mailto:nrotem at apple.com>>
>   wrote:
>
>> Richard,
>>
>> The assertion that you suggested that we remove is about something different.
>> It checks that the result of the select node is legalized before the
>> condition.  Can you show us the SDNode that fails on this assertion ?
>
> Not at the moment… ;-) With your fix to visitSIGN_EXTEND, this problem seems to
> have disappeared...

in that case can you please revert this patch if you applied it.

Thanks, Duncan.

>
>> Thanks,
>> Nadav
>>
>> On Mar 12, 2013, at 9:25 AM, Duncan Sands <baldrick at free.fr
>> <mailto:baldrick at free.fr>> wrote:
>>
>>> Hi Richard,
>>>
>>> On 12/03/13 16:00, Relph, Richard wrote:
>>>> DAGTypeLegalizer::SplitRes_SELECT() currently does an assert if the
>>>> condition is not of type MVT::i1. This patch uses the existing type of the
>>>> condition to generate the type for the split conditions instead of a fixed i1.
>>>> This is an issue for us when trying to legalize a 8x or 16x vector to a 4x
>>>> type… it isn't the case that we always have an MVT::i1 condition coming in.
>>>
>>> if the select condition is a vector then you should be using a vselect node
>>> rather than a select node.  So I think this patch is wrong and the real problem
>>> is that the wrong select node type is being generated somewhere.
>>>
>>> Ciao, Duncan.
>>>
>>>>
>>>> Index: lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
>>>> ===================================================================
>>>> --- lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp(revision 176837)
>>>> +++ lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp(working copy)
>>>> @@ -490,10 +490,10 @@
>>>>    SDValue Cond = N->getOperand(0);
>>>>    CL = CH = Cond;
>>>>    if (Cond.getValueType().isVector()) {
>>>> -    assert(Cond.getValueType().getVectorElementType() == MVT::i1 &&
>>>> -           "Condition legalized before result?");
>>>>      unsigned NumElements = Cond.getValueType().getVectorNumElements();
>>>> -    EVT VCondTy = EVT::getVectorVT(*DAG.getContext(), MVT::i1, NumElements
>>>> / 2);
>>>> +    EVT VCondTy = EVT::getVectorVT(*DAG.getContext(),
>>>> +                                   Cond.getValueType().getVectorElementType(),
>>>> +                                   NumElements / 2);
>>>>      CL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
>>>>                       DAG.getIntPtrConstant(0));
>>>>      CH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
>>>>
>>>>
>>>>
>>>> _______________________________________________
>>>> llvm-commits mailing list
>>>> llvm-commits at cs.uiuc.edu <mailto:llvm-commits at cs.uiuc.edu>
>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>