[llvm] r176624 - R600/SI: remove SGPR address space v2
Christian Konig
christian.koenig at amd.com
Thu Mar 7 01:03:59 PST 2013
Author: ckoenig
Date: Thu Mar 7 03:03:59 2013
New Revision: 176624
URL: http://llvm.org/viewvc/llvm-project?rev=176624&view=rev
Log:
R600/SI: remove SGPR address space v2
v2: fix R600 regressions
Signed-off-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
Modified:
llvm/trunk/lib/Target/R600/AMDIL.h
llvm/trunk/lib/Target/R600/R600ISelLowering.cpp
llvm/trunk/lib/Target/R600/SIISelLowering.cpp
llvm/trunk/lib/Target/R600/SIISelLowering.h
llvm/trunk/lib/Target/R600/SIInstructions.td
Modified: llvm/trunk/lib/Target/R600/AMDIL.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDIL.h?rev=176624&r1=176623&r2=176624&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/AMDIL.h (original)
+++ llvm/trunk/lib/Target/R600/AMDIL.h Thu Mar 7 03:03:59 2013
@@ -96,24 +96,23 @@ enum AddressSpaces {
ADDRESS_NONE = 5, ///< Address space for unknown memory.
PARAM_D_ADDRESS = 6, ///< Address space for direct addressible parameter memory (CONST0)
PARAM_I_ADDRESS = 7, ///< Address space for indirect addressible parameter memory (VTX1)
- USER_SGPR_ADDRESS = 8, ///< Address space for USER_SGPRS on SI
- CONSTANT_BUFFER_0 = 9,
- CONSTANT_BUFFER_1 = 10,
- CONSTANT_BUFFER_2 = 11,
- CONSTANT_BUFFER_3 = 12,
- CONSTANT_BUFFER_4 = 13,
- CONSTANT_BUFFER_5 = 14,
- CONSTANT_BUFFER_6 = 15,
- CONSTANT_BUFFER_7 = 16,
- CONSTANT_BUFFER_8 = 17,
- CONSTANT_BUFFER_9 = 18,
- CONSTANT_BUFFER_10 = 19,
- CONSTANT_BUFFER_11 = 20,
- CONSTANT_BUFFER_12 = 21,
- CONSTANT_BUFFER_13 = 22,
- CONSTANT_BUFFER_14 = 23,
- CONSTANT_BUFFER_15 = 24,
- LAST_ADDRESS = 25
+ CONSTANT_BUFFER_0 = 8,
+ CONSTANT_BUFFER_1 = 9,
+ CONSTANT_BUFFER_2 = 10,
+ CONSTANT_BUFFER_3 = 11,
+ CONSTANT_BUFFER_4 = 12,
+ CONSTANT_BUFFER_5 = 13,
+ CONSTANT_BUFFER_6 = 14,
+ CONSTANT_BUFFER_7 = 15,
+ CONSTANT_BUFFER_8 = 16,
+ CONSTANT_BUFFER_9 = 17,
+ CONSTANT_BUFFER_10 = 18,
+ CONSTANT_BUFFER_11 = 19,
+ CONSTANT_BUFFER_12 = 20,
+ CONSTANT_BUFFER_13 = 21,
+ CONSTANT_BUFFER_14 = 22,
+ CONSTANT_BUFFER_15 = 23,
+ LAST_ADDRESS = 24
};
} // namespace AMDGPUAS
Modified: llvm/trunk/lib/Target/R600/R600ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600ISelLowering.cpp?rev=176624&r1=176623&r2=176624&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/R600ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/R600/R600ISelLowering.cpp Thu Mar 7 03:03:59 2013
@@ -941,7 +941,8 @@ SDValue R600TargetLowering::LowerLOAD(SD
// non constant ptr cant be folded, keeps it as a v4f32 load
Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
- DAG.getConstant(LoadNode->getAddressSpace() - 9, MVT::i32)
+ DAG.getConstant(LoadNode->getAddressSpace() -
+ AMDGPUAS::CONSTANT_BUFFER_0, MVT::i32)
);
}
Modified: llvm/trunk/lib/Target/R600/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIISelLowering.cpp?rev=176624&r1=176623&r2=176624&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIISelLowering.cpp Thu Mar 7 03:03:59 2013
@@ -62,11 +62,6 @@ SITargetLowering::SITargetLowering(Targe
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
- // We need to custom lower loads from the USER_SGPR address space, so we can
- // add the SGPRs as livein registers.
- setOperationAction(ISD::LOAD, MVT::i32, Custom);
- setOperationAction(ISD::LOAD, MVT::i64, Custom);
-
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
@@ -245,7 +240,6 @@ SDValue SITargetLowering::LowerOperation
switch (Op.getOpcode()) {
default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
case ISD::BRCOND: return LowerBRCOND(Op, DAG);
- case ISD::LOAD: return LowerLOAD(Op, DAG);
case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
case ISD::INTRINSIC_WO_CHAIN: {
unsigned IntrinsicID =
@@ -357,47 +351,6 @@ SDValue SITargetLowering::LowerBRCOND(SD
return Chain;
}
-SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
- EVT VT = Op.getValueType();
- LoadSDNode *Ptr = dyn_cast<LoadSDNode>(Op);
-
- assert(Ptr);
-
- unsigned AddrSpace = Ptr->getPointerInfo().getAddrSpace();
-
- // We only need to lower USER_SGPR address space loads
- if (AddrSpace != AMDGPUAS::USER_SGPR_ADDRESS) {
- return SDValue();
- }
-
- // Loads from the USER_SGPR address space can only have constant value
- // pointers.
- ConstantSDNode *BasePtr = dyn_cast<ConstantSDNode>(Ptr->getBasePtr());
- assert(BasePtr);
-
- unsigned TypeDwordWidth = VT.getSizeInBits() / 32;
- const TargetRegisterClass * dstClass;
- switch (TypeDwordWidth) {
- default:
- assert(!"USER_SGPR value size not implemented");
- return SDValue();
- case 1:
- dstClass = &AMDGPU::SReg_32RegClass;
- break;
- case 2:
- dstClass = &AMDGPU::SReg_64RegClass;
- break;
- }
- uint64_t Index = BasePtr->getZExtValue();
- assert(Index % TypeDwordWidth == 0 && "USER_SGPR not properly aligned");
- unsigned SGPRIndex = Index / TypeDwordWidth;
- unsigned Reg = dstClass->getRegister(SGPRIndex);
-
- DAG.ReplaceAllUsesOfValueWith(Op, CreateLiveInRegister(DAG, dstClass, Reg,
- VT));
- return SDValue();
-}
-
SDValue SITargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1);
Modified: llvm/trunk/lib/Target/R600/SIISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIISelLowering.h?rev=176624&r1=176623&r2=176624&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIISelLowering.h (original)
+++ llvm/trunk/lib/Target/R600/SIISelLowering.h Thu Mar 7 03:03:59 2013
@@ -31,7 +31,6 @@ class SITargetLowering : public AMDGPUTa
void LowerSI_WQM(MachineInstr *MI, MachineBasicBlock &BB,
MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
- SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
Modified: llvm/trunk/lib/Target/R600/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstructions.td?rev=176624&r1=176623&r2=176624&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/R600/SIInstructions.td Thu Mar 7 03:03:59 2013
@@ -1337,9 +1337,8 @@ def : Pat <
/********** ===================== **********/
def : Pat <
- (int_SI_fs_interp_constant imm:$attr_chan, imm:$attr, SReg_32:$params),
- (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr,
- (S_MOV_B32 SReg_32:$params))
+ (int_SI_fs_interp_constant imm:$attr_chan, imm:$attr, M0Reg:$params),
+ (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, M0Reg:$params)
>;
def : Pat <
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