[PING] Improved TableGen support for PowerPC pre-inc operand matching

[Jakob Stoklund Olesen]

On Feb 25, 2013, at 7:57 AM, Ulrich Weigand <Ulrich.Weigand at de.ibm.com> wrote:

> 
> 
> Jakub,
> 
> I'm still working on asm parser support for PowerPC, and it turns out a
> couple of TableGen changes would make the back-end implementation
> significantly cleaner.  In particular, a couple of weeks ago I posted a
> patch to extend TableGen code to allow writing "Pat" patterns that produce
> an output instruction having a single operand (with multiple sub-operands)
> by providing the sub-operands as distinct operands at the pattern level:
> http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130204/164592.html
> 
> [ Note that I've continued to investigate the X86 TLS pattern I've refered
> to in that mail.  As far as I can see, this pattern is really simply
> broken, but then again it never gets used, since code matching (load (i64
> (X86Wrapper tglobaltlsaddr :$dst))) can never be generated by the X86
> back-end. So I'd now indeed suggest to simply remove the pattern.  ]
> 
> I'd really appreciate a review of those TableGen changes.   Do you think
> this is the correct approach, or do you have any other suggestions?
> Thanks for your help!

Hi Ulrich,

This generally looks good, but please add some documentation of the feature.

Also, please break the target changes into separate patches. The X86 issue seems almost unrelated.

/jakob