[PATCH 3/9] R600/SI: fix VOP3b encoding

[Tom Stellard]

On Mon, Feb 25, 2013 at 03:48:58PM +0100, Christian König wrote:
> From: Christian König <christian.koenig at amd.com>
> 
> Signed-off-by: Christian König <christian.koenig at amd.com>
> ---
>  lib/Target/R600/SIInstrInfo.td    |   22 ++++++++++++++++++++++
>  lib/Target/R600/SIInstructions.td |   14 ++++++++------
>  2 files changed, 30 insertions(+), 6 deletions(-)
> 
> diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
> index 99168ce..d379185 100644
> --- a/lib/Target/R600/SIInstrInfo.td
> +++ b/lib/Target/R600/SIInstrInfo.td
> @@ -51,6 +51,7 @@ class InlineImm <ValueType vt> : ImmLeaf <vt, [{
>  
>  def SIOperand {
>    int ZERO = 0x80;
> +  int VCC = 0x6A;
>  }
>  
>  class GPR4Align <RegisterClass rc> : Operand <vAny> {
> @@ -195,6 +196,27 @@ multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern>
>  multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern>
>    : VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern>;
>  
> +multiclass VOP2b_32 <bits<6> op, string opName, list<dag> pattern> {
> +
> +  def _e32 : VOP2 <
> +    op, (outs VReg_32:$dst), (ins VSrc_32:$src0, VReg_32:$src1),
> +    opName#"_e32 $dst, $src0, $src1", pattern
> +  >;
> +
> +  def _e64 : VOP3b <
> +    {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
> +    (outs VReg_32:$dst),
> +    (ins VSrc_32:$src0, VReg_32:$src1,
> +         i32imm:$abs, i32imm:$clamp,
> +         i32imm:$omod, i32imm:$neg),
> +    opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", []
> +  > {
> +    let SRC2 = SIOperand.ZERO;
> +    // Hardcode SDST to VCC for now
> +    let SDST = SIOperand.VCC;

Why this this hardcoded to VCC?

> +  }
> +}
> +
>  multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
>                          string opName, ValueType vt, PatLeaf cond> {
>  
> diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
> index 9701d19..f999025 100644
> --- a/lib/Target/R600/SIInstructions.td
> +++ b/lib/Target/R600/SIInstructions.td
> @@ -805,17 +805,19 @@ defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>;
>  //defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>;
>  //defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>;
>  let Defs = [VCC] in { // Carry-out goes to VCC
> -defm V_ADD_I32 : VOP2_32 <0x00000025, "V_ADD_I32",
> +defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32",
>    [(set VReg_32:$dst, (add (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))]
>  >;
> -defm V_SUB_I32 : VOP2_32 <0x00000026, "V_SUB_I32",
> +defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32",
>    [(set VReg_32:$dst, (sub (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))]
>  >;
> +defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", []>;
> +let Uses = [VCC] in { // Carry-out comes from VCC
> +defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", []>;
> +defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", []>;
> +defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", []>;
> +} // End Uses = [VCC]
>  } // End Defs = [VCC]
> -defm V_SUBREV_I32 : VOP2_32 <0x00000027, "V_SUBREV_I32", []>;
> -defm V_ADDC_U32 : VOP2_32 <0x00000028, "V_ADDC_U32", []>;
> -defm V_SUBB_U32 : VOP2_32 <0x00000029, "V_SUBB_U32", []>;
> -defm V_SUBBREV_U32 : VOP2_32 <0x0000002a, "V_SUBBREV_U32", []>;
>  defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>;
>  ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>;
>  ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>;
> -- 
> 1.7.10.4
> 
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