[PATCH 2/9] R600/SI: fix and cleanup SI register definition
Tom Stellard
tom at stellard.net
Mon Feb 25 17:58:42 PST 2013
On Mon, Feb 25, 2013 at 03:48:57PM +0100, Christian König wrote:
> From: Christian König <christian.koenig at amd.com>
>
> Prevent producing real strange tablegen code by using
> proper register sizes, alignments and hierarchy.
>
> Also cleanup the unused definitions and add some comments.
>
> Signed-off-by: Christian König <christian.koenig at amd.com>
> ---
> lib/Target/R600/SIInstructions.td | 5 +-
> lib/Target/R600/SIRegisterInfo.td | 117 +++++++++++++++++++++----------------
> 2 files changed, 69 insertions(+), 53 deletions(-)
>
> diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
> index 907cf49..9701d19 100644
> --- a/lib/Target/R600/SIInstructions.td
> +++ b/lib/Target/R600/SIInstructions.td
> @@ -918,14 +918,15 @@ def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32", []>;
> def S_CSELECT_B32 : SOP2 <
> 0x0000000a, (outs SReg_32:$dst),
> (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32",
> - [(set (i32 SReg_32:$dst), (select SCCReg:$scc, SReg_32:$src0, SReg_32:$src1))]
> + [(set (i32 SReg_32:$dst), (select (i1 SCCReg:$scc),
> + SReg_32:$src0, SReg_32:$src1))]
> >;
>
> def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>;
>
> // f32 pattern for S_CSELECT_B32
> def : Pat <
> - (f32 (select SCCReg:$scc, SReg_32:$src0, SReg_32:$src1)),
> + (f32 (select (i1 SCCReg:$scc), SReg_32:$src0, SReg_32:$src1)),
> (S_CSELECT_B32 SReg_32:$src0, SReg_32:$src1, SCCReg:$scc)
> >;
>
> diff --git a/lib/Target/R600/SIRegisterInfo.td b/lib/Target/R600/SIRegisterInfo.td
> index ab36b87..7eec1a6 100644
> --- a/lib/Target/R600/SIRegisterInfo.td
> +++ b/lib/Target/R600/SIRegisterInfo.td
> @@ -1,30 +1,40 @@
> +//===-- SIRegisterInfo.td - SI Register defs ---------------*- tablegen -*-===//
> +//
> +// The LLVM Compiler Infrastructure
> +//
> +// This file is distributed under the University of Illinois Open Source
> +// License. See LICENSE.TXT for details.
> +//
> +//===----------------------------------------------------------------------===//
> +
> +//===----------------------------------------------------------------------===//
> +// Declarations that describe the SI registers
> +//===----------------------------------------------------------------------===//
>
> class SIReg <string n, bits<16> encoding = 0> : Register<n> {
> let Namespace = "AMDGPU";
> let HWEncoding = encoding;
> }
>
> -class SI_64 <string n, list<Register> subregs, bits<16> encoding> : RegisterWithSubRegs<n, subregs> {
> - let Namespace = "AMDGPU";
> - let SubRegIndices = [sub0, sub1];
> - let HWEncoding = encoding;
> -}
> -
> -class SGPR_32 <bits<16> num, string name> : SIReg<name, num>;
> -
> -class VGPR_32 <bits<16> num, string name> : SIReg<name, num> {
> - let HWEncoding{8} = 1;
> -}
> -
> // Special Registers
> def VCC : SIReg<"VCC", 106>;
> -def EXEC_LO : SIReg <"EXEC LO", 126>;
> -def EXEC_HI : SIReg <"EXEC HI", 127>;
> -def EXEC : SI_64<"EXEC", [EXEC_LO, EXEC_HI], 126>;
> +def EXEC : SIReg<"EXEC", 126>;
> def SCC : SIReg<"SCC", 253>;
> def M0 : SIReg <"M0", 124>;
>
> -//Interpolation registers
> +// SGPR registers
> +foreach Index = 0-101 in {
> + def SGPR#Index : SIReg <"SGPR"#Index, Index>;
> +}
> +
> +// VGPR registers
> +foreach Index = 0-255 in {
> + def VGPR#Index : SIReg <"VGPR"#Index, Index> {
> + let HWEncoding{8} = 1;
> + }
> +}
> +
> +// virtual Interpolation registers
> def PERSP_SAMPLE_I : SIReg <"PERSP_SAMPLE_I">;
> def PERSP_SAMPLE_J : SIReg <"PERSP_SAMPLE_J">;
> def PERSP_CENTER_I : SIReg <"PERSP_CENTER_I">;
> @@ -50,11 +60,11 @@ def ANCILLARY : SIReg <"ANCILLARY">;
> def SAMPLE_COVERAGE : SIReg <"SAMPLE_COVERAGE">;
> def POS_FIXED_PT : SIReg <"POS_FIXED_PT">;
>
> -// SGPR 32-bit registers
> -foreach Index = 0-101 in {
> - def SGPR#Index : SGPR_32 <Index, "SGPR"#Index>;
> -}
> +//===----------------------------------------------------------------------===//
> +// Groupings using register classes and tuples
> +//===----------------------------------------------------------------------===//
>
> +// SGPR 32-bit registers
> def SGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
> (add (sequence "SGPR%u", 0, 101))>;
>
> @@ -82,10 +92,6 @@ def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
> (add (decimate (rotl SGPR_32, 7), 8))]>;
>
> // VGPR 32-bit registers
> -foreach Index = 0-255 in {
> - def VGPR#Index : VGPR_32 <Index, "VGPR"#Index>;
> -}
> -
> def VGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
> (add (sequence "VGPR%u", 0, 255))>;
>
> @@ -132,20 +138,50 @@ def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
> (add (rotl VGPR_32, 14)),
> (add (rotl VGPR_32, 15))]>;
>
> +//===----------------------------------------------------------------------===//
> +// Register classes used as source and destination
> +//===----------------------------------------------------------------------===//
> +
> +// Special register classes for predicates and the M0 register
> +def SCCReg : RegisterClass<"AMDGPU", [i32, i1], 32, (add SCC)>;
> +def VCCReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add VCC)>;
> +def EXECReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add EXEC)>;
> +def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
> +
> // Register class for all scalar registers (SGPRs + Special Registers)
> def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
> - (add SGPR_32, M0, EXEC_LO, EXEC_HI)
> + (add SGPR_32, M0Reg)
> >;
>
> -def SReg_64 : RegisterClass<"AMDGPU", [i1, i64], 64, (add SGPR_64, VCC, EXEC)>;
> +def SReg_64 : RegisterClass<"AMDGPU", [i64, i1], 64,
> + (add SGPR_64, VCCReg, EXECReg)
> +>;
I noticed that there are several classes that have an extra i1 type. I
don't think this is necessary for the SGPR classes and it may not even
be necessary for VGPR classes. Do you think you could clean these up
too?
-Tom
>
> def SReg_128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add SGPR_128)>;
>
> def SReg_256 : RegisterClass<"AMDGPU", [v8i32], 256, (add SGPR_256)>;
>
> // Register class for all vector registers (VGPRs + Interploation Registers)
> -def VReg_32 : RegisterClass<"AMDGPU", [f32, i32, v1i32], 32,
> - (add VGPR_32,
> +def VReg_32 : RegisterClass<"AMDGPU", [f32, i32, v1i32], 32, (add VGPR_32)>;
> +
> +def VReg_64 : RegisterClass<"AMDGPU", [i64, v2i32], 64, (add VGPR_64)>;
> +
> +def VReg_128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add VGPR_128)>;
> +
> +def VReg_256 : RegisterClass<"AMDGPU", [v8i32], 256, (add VGPR_256)>;
> +
> +def VReg_512 : RegisterClass<"AMDGPU", [v16i32], 512, (add VGPR_512)>;
> +
> +//===----------------------------------------------------------------------===//
> +// [SV]Src_* register classes, can have either an immediate or an register
> +//===----------------------------------------------------------------------===//
> +
> +def SSrc_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add SReg_32)>;
> +
> +def SSrc_64 : RegisterClass<"AMDGPU", [i64, i1], 64, (add SReg_64)>;
> +
> +def VSrc_32 : RegisterClass<"AMDGPU", [i32, f32], 32,
> + (add VReg_32, SReg_32,
> PERSP_SAMPLE_I, PERSP_SAMPLE_J,
> PERSP_CENTER_I, PERSP_CENTER_J,
> PERSP_CENTROID_I, PERSP_CENTROID_J,
> @@ -162,29 +198,8 @@ def VReg_32 : RegisterClass<"AMDGPU", [f32, i32, v1i32], 32,
> ANCILLARY,
> SAMPLE_COVERAGE,
> POS_FIXED_PT
> - )
> + )
> >;
>
> -def VReg_64 : RegisterClass<"AMDGPU", [i64, v2i32], 64, (add VGPR_64)>;
> -
> -def VReg_128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add VGPR_128)>;
> -
> -def VReg_256 : RegisterClass<"AMDGPU", [v8i32], 256, (add VGPR_256)>;
> -
> -def VReg_512 : RegisterClass<"AMDGPU", [v16i32], 512, (add VGPR_512)>;
> -
> -// [SV]Src_* operands can have either an immediate or an register
> -def SSrc_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add SReg_32)>;
> -
> -def SSrc_64 : RegisterClass<"AMDGPU", [i1, i64], 64, (add SReg_64)>;
> -
> -def VSrc_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VReg_32, SReg_32)>;
> -
> -def VSrc_64 : RegisterClass<"AMDGPU", [i64], 64, (add SReg_64, VReg_64)>;
> -
> -// Special register classes for predicates and the M0 register
> -def SCCReg : RegisterClass<"AMDGPU", [i1], 1, (add SCC)>;
> -def VCCReg : RegisterClass<"AMDGPU", [i1], 1, (add VCC)>;
> -def EXECReg : RegisterClass<"AMDGPU", [i1], 1, (add EXEC)>;
> -def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
> +def VSrc_64 : RegisterClass<"AMDGPU", [i64], 64, (add VReg_64, SReg_64)>;
>
> --
> 1.7.10.4
>
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