[llvm] r175911 - x86_64: designate most general purpose and SSE registers as callee save under coldcc

[Anna Zaks]

Peter,

The new test is failing on one of our builders:

http://lab.llvm.org:8011/console

******************** TEST 'LLVM :: CodeGen/X86/coldcc64.ll' FAILED ********************
Script:
--
./clang-build/Release+Asserts/bin/llc < ./llvm/test/CodeGen/X86/coldcc64.ll | ./clang-build/Release+Asserts/bin/FileCheck ./llvm/test/CodeGen/X86/coldcc64.ll
--
Exit Code: 1
Command Output (stderr):
--
./llvm/test/CodeGen/X86/coldcc64.ll:20:10: error: expected string not found in input
; CHECK: vmovaps %xmm15
         ^
<stdin>:49:1: note: scanning from here
.Ltmp28:
^
<stdin>:83:2: note: possible intended match here
 movaps %xmm15, -40(%rsp) # 16-byte Spill
 ^
--
On Feb 22, 2013, at 11:19 AM, Peter Collingbourne <peter at pcc.me.uk> wrote:

> Author: pcc
> Date: Fri Feb 22 13:19:44 2013
> New Revision: 175911
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=175911&view=rev
> Log:
> x86_64: designate most general purpose and SSE registers as callee save under coldcc
> 
> Added:
>    llvm/trunk/test/CodeGen/X86/coldcc64.ll
> Modified:
>    llvm/trunk/lib/Target/X86/X86CallingConv.td
>    llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
> 
> Modified: llvm/trunk/lib/Target/X86/X86CallingConv.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CallingConv.td?rev=175911&r1=175910&r2=175911&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86CallingConv.td (original)
> +++ llvm/trunk/lib/Target/X86/X86CallingConv.td Fri Feb 22 13:19:44 2013
> @@ -519,6 +519,9 @@ def CSR_64EHRet : CalleeSavedRegs<(add R
> def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
>                                      (sequence "XMM%u", 6, 15))>;
> 
> +def CSR_MostRegs_64 : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
> +                                           R11, R12, R13, R14, R15, RBP,
> +                                           (sequence "XMM%u", 0, 15))>;
> 
> // Standard C + YMM6-15
> def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
> 
> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=175911&r1=175910&r2=175911&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Fri Feb 22 13:19:44 2013
> @@ -235,38 +235,40 @@ X86RegisterInfo::getRegPressureLimit(con
> 
> const uint16_t *
> X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
> -  bool callsEHReturn = false;
> -  bool ghcCall = false;
> -  bool oclBiCall = false;
> -  bool hipeCall = false;
> -  bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
> -
> -  if (MF) {
> -    callsEHReturn = MF->getMMI().callsEHReturn();
> -    const Function *F = MF->getFunction();
> -    ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
> -    oclBiCall = (F ? F->getCallingConv() == CallingConv::Intel_OCL_BI : false);
> -    hipeCall = (F ? F->getCallingConv() == CallingConv::HiPE : false);
> -  }
> -
> -  if (ghcCall || hipeCall)
> +  switch (MF->getFunction()->getCallingConv()) {
> +  case CallingConv::GHC:
> +  case CallingConv::HiPE:
>     return CSR_NoRegs_SaveList;
> -  if (oclBiCall) {
> +
> +  case CallingConv::Intel_OCL_BI: {
> +    bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
>     if (HasAVX && IsWin64)
> -        return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
> +      return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
>     if (HasAVX && Is64Bit)
> -        return CSR_64_Intel_OCL_BI_AVX_SaveList;
> +      return CSR_64_Intel_OCL_BI_AVX_SaveList;
>     if (!HasAVX && !IsWin64 && Is64Bit)
> -        return CSR_64_Intel_OCL_BI_SaveList;
> +      return CSR_64_Intel_OCL_BI_SaveList;
> +    break;
>   }
> +
> +  case CallingConv::Cold:
> +    if (Is64Bit)
> +      return CSR_MostRegs_64_SaveList;
> +    break;
> +
> +  default:
> +    break;
> +  }
> +
> +  bool CallsEHReturn = MF->getMMI().callsEHReturn();
>   if (Is64Bit) {
>     if (IsWin64)
>       return CSR_Win64_SaveList;
> -    if (callsEHReturn)
> +    if (CallsEHReturn)
>       return CSR_64EHRet_SaveList;
>     return CSR_64_SaveList;
>   }
> -  if (callsEHReturn)
> +  if (CallsEHReturn)
>     return CSR_32EHRet_SaveList;
>   return CSR_32_SaveList;
> }
> @@ -287,6 +289,8 @@ X86RegisterInfo::getCallPreservedMask(Ca
>     return CSR_NoRegs_RegMask;
>   if (!Is64Bit)
>     return CSR_32_RegMask;
> +  if (CC == CallingConv::Cold)
> +    return CSR_MostRegs_64_RegMask;
>   if (IsWin64)
>     return CSR_Win64_RegMask;
>   return CSR_64_RegMask;
> 
> Added: llvm/trunk/test/CodeGen/X86/coldcc64.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/coldcc64.ll?rev=175911&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/coldcc64.ll (added)
> +++ llvm/trunk/test/CodeGen/X86/coldcc64.ll Fri Feb 22 13:19:44 2013
> @@ -0,0 +1,24 @@
> +; RUN: llc < %s | FileCheck %s
> +
> +target triple = "x86_64-linux-gnu"
> +
> +define coldcc void @foo() {
> +; CHECK: pushq %rbp
> +; CHECK: pushq %r15
> +; CHECK: pushq %r14
> +; CHECK: pushq %r13
> +; CHECK: pushq %r12
> +; CHECK: pushq %r11
> +; CHECK: pushq %r10
> +; CHECK: pushq %r9
> +; CHECK: pushq %r8
> +; CHECK: pushq %rdi
> +; CHECK: pushq %rsi
> +; CHECK: pushq %rdx
> +; CHECK: pushq %rcx
> +; CHECK: pushq %rbx
> +; CHECK: vmovaps %xmm15
> +; CHECK: vmovaps %xmm0
> +  call void asm sideeffect "", "~{xmm15},~{xmm0},~{rbp},~{r15},~{r14},~{r13},~{r12},~{r11},~{r10},~{r9},~{r8},~{rdi},~{rsi},~{rdx},~{rcx},~{rbx}"()
> +  ret void
> +}
> 
> 
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