[llvm] r175767 - Large code model support for PowerPC.
Bill Schmidt
wschmidt at linux.vnet.ibm.com
Thu Feb 21 09:12:28 PST 2013
Author: wschmidt
Date: Thu Feb 21 11:12:27 2013
New Revision: 175767
URL: http://llvm.org/viewvc/llvm-project?rev=175767&view=rev
Log:
Large code model support for PowerPC.
Large code model is identical to medium code model except that the
addis/addi sequence for "local" accesses is never used. All accesses
use the addis/ld sequence.
The coding changes are straightforward; most of the patch is taken up
with creating variants of the medium model tests for large model.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
llvm/trunk/test/CodeGen/PowerPC/mcm-1.ll
llvm/trunk/test/CodeGen/PowerPC/mcm-2.ll
llvm/trunk/test/CodeGen/PowerPC/mcm-3.ll
llvm/trunk/test/CodeGen/PowerPC/mcm-4.ll
llvm/trunk/test/CodeGen/PowerPC/mcm-5.ll
llvm/trunk/test/CodeGen/PowerPC/mcm-6.ll
llvm/trunk/test/CodeGen/PowerPC/mcm-7.ll
llvm/trunk/test/CodeGen/PowerPC/mcm-8.ll
llvm/trunk/test/CodeGen/PowerPC/mcm-9.ll
llvm/trunk/test/CodeGen/PowerPC/mcm-obj.ll
Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=175767&r1=175766&r2=175767&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Thu Feb 21 11:12:27 2013
@@ -464,12 +464,15 @@ void PPCAsmPrinter::EmitInstruction(cons
// associated TOC entry. Otherwise reference the symbol directly.
TmpInst.setOpcode(PPC::LDrs);
const MachineOperand &MO = MI->getOperand(1);
- assert((MO.isGlobal() || MO.isJTI()) && "Invalid operand for LDtocL!");
+ assert((MO.isGlobal() || MO.isJTI() || MO.isCPI()) &&
+ "Invalid operand for LDtocL!");
MCSymbol *MOSymbol = 0;
if (MO.isJTI())
MOSymbol = lookUpOrCreateTOCEntry(GetJTISymbol(MO.getIndex()));
- else {
+ else if (MO.isCPI())
+ MOSymbol = GetCPISymbol(MO.getIndex());
+ else if (MO.isGlobal()) {
const GlobalValue *GValue = MO.getGlobal();
const GlobalAlias *GAlias = dyn_cast<GlobalAlias>(GValue);
const GlobalValue *RealGValue = GAlias ?
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=175767&r1=175766&r2=175767&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu Feb 21 11:12:27 2013
@@ -1281,16 +1281,17 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *
case PPCISD::TOC_ENTRY: {
assert (PPCSubTarget.isPPC64() && "Only supported for 64-bit ABI");
- // For medium code model, we generate two instructions as described
- // below. Otherwise we allow SelectCodeCommon to handle this, selecting
- // one of LDtoc, LDtocJTI, and LDtocCPT.
- if (TM.getCodeModel() != CodeModel::Medium)
+ // For medium and large code model, we generate two instructions as
+ // described below. Otherwise we allow SelectCodeCommon to handle this,
+ // selecting one of LDtoc, LDtocJTI, and LDtocCPT.
+ CodeModel::Model CModel = TM.getCodeModel();
+ if (CModel != CodeModel::Medium && CModel != CodeModel::Large)
break;
// The first source operand is a TargetGlobalAddress or a
// TargetJumpTable. If it is an externally defined symbol, a symbol
// with common linkage, a function address, or a jump table address,
- // we generate:
+ // or if we are generating code for large code model, we generate:
// LDtocL(<ga:@sym>, ADDIStocHA(%X2, <ga:@sym>))
// Otherwise we generate:
// ADDItocL(ADDIStocHA(%X2, <ga:@sym>), <ga:@sym>)
@@ -1299,7 +1300,7 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *
SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,
TOCbase, GA);
- if (isa<JumpTableSDNode>(GA))
+ if (isa<JumpTableSDNode>(GA) || CModel == CodeModel::Large)
return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
SDValue(Tmp, 0));
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=175767&r1=175766&r2=175767&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Thu Feb 21 11:12:27 2013
@@ -258,13 +258,14 @@ namespace llvm {
/// or i32.
LBRX,
- /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium code model, produces
- /// an ADDIS8 instruction that adds the TOC base register to sym at toc@ha.
+ /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model,
+ /// produces an ADDIS8 instruction that adds the TOC base register to
+ /// sym at toc@ha.
ADDIS_TOC_HA,
- /// G8RC = LD_TOC_L Symbol, G8RReg - For medium code model, produces a
- /// LD instruction with base register G8RReg and offset sym at toc@l.
- /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
+ /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model,
+ /// produces a LD instruction with base register G8RReg and offset
+ /// sym at toc@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
LD_TOC_L,
/// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=175767&r1=175766&r2=175767&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Thu Feb 21 11:12:27 2013
@@ -701,7 +701,7 @@ def : Pat<(PPCload ixaddr:$src),
def : Pat<(PPCload xaddr:$src),
(LDX xaddr:$src)>;
-// Support for medium code model.
+// Support for medium and large code model.
def ADDIStocHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tocentry:$disp),
"#ADDIStocHA",
[(set G8RC:$rD,
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=175767&r1=175766&r2=175767&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Thu Feb 21 11:12:27 2013
@@ -181,7 +181,7 @@ def PPClarx : SDNode<"PPCISD::LARX"
def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
[SDNPHasChain, SDNPMayStore]>;
-// Instructions to support medium code model
+// Instructions to support medium and large code model
def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
Modified: llvm/trunk/test/CodeGen/PowerPC/mcm-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/mcm-1.ll?rev=175767&r1=175766&r2=175767&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/mcm-1.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/mcm-1.ll Thu Feb 21 11:12:27 2013
@@ -1,6 +1,7 @@
; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s
-; Test correct code generation for medium code model (32-bit TOC offsets)
+; Test correct code generation for medium and large code model
; for loading and storing an external variable.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
Modified: llvm/trunk/test/CodeGen/PowerPC/mcm-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/mcm-2.ll?rev=175767&r1=175766&r2=175767&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/mcm-2.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/mcm-2.ll Thu Feb 21 11:12:27 2013
@@ -1,6 +1,7 @@
-; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck -check-prefix=MEDIUM %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck -check-prefix=LARGE %s
-; Test correct code generation for medium code model (32-bit TOC offsets)
+; Test correct code generation for medium and large code model
; for loading and storing a static variable scoped to a function.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
@@ -16,11 +17,21 @@ entry:
ret i32 %0
}
-; CHECK: test_fn_static:
-; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc at ha
-; CHECK: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc at l
-; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
-; CHECK: stw {{[0-9]+}}, 0([[REG2]])
-; CHECK: .type [[VAR]], at object
-; CHECK: .local [[VAR]]
-; CHECK: .comm [[VAR]],4,4
+; MEDIUM: test_fn_static:
+; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc at ha
+; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc at l
+; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]])
+; MEDIUM: stw {{[0-9]+}}, 0([[REG2]])
+; MEDIUM: .type [[VAR]], at object
+; MEDIUM: .local [[VAR]]
+; MEDIUM: .comm [[VAR]],4,4
+
+; LARGE: test_fn_static:
+; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc at ha
+; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc at l([[REG1]])
+; LARGE: lwz {{[0-9]+}}, 0([[REG2]])
+; LARGE: stw {{[0-9]+}}, 0([[REG2]])
+; LARGE: .type [[VAR]], at object
+; LARGE: .local [[VAR]]
+; LARGE: .comm [[VAR]],4,4
+
Modified: llvm/trunk/test/CodeGen/PowerPC/mcm-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/mcm-3.ll?rev=175767&r1=175766&r2=175767&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/mcm-3.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/mcm-3.ll Thu Feb 21 11:12:27 2013
@@ -1,6 +1,7 @@
-; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck -check-prefix=MEDIUM %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck -check-prefix=LARGE %s
-; Test correct code generation for medium code model (32-bit TOC offsets)
+; Test correct code generation for medium and large code model
; for loading and storing a file-scope static variable.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
@@ -16,13 +17,25 @@ entry:
ret i32 %0
}
-; CHECK: test_file_static:
-; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc at ha
-; CHECK: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc at l
-; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
-; CHECK: stw {{[0-9]+}}, 0([[REG2]])
-; CHECK: .type [[VAR]], at object
-; CHECK: .data
-; CHECK: .globl [[VAR]]
-; CHECK: [[VAR]]:
-; CHECK: .long 5
+; MEDIUM: test_file_static:
+; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc at ha
+; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc at l
+; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]])
+; MEDIUM: stw {{[0-9]+}}, 0([[REG2]])
+; MEDIUM: .type [[VAR]], at object
+; MEDIUM: .data
+; MEDIUM: .globl [[VAR]]
+; MEDIUM: [[VAR]]:
+; MEDIUM: .long 5
+
+; LARGE: test_file_static:
+; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc at ha
+; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc at l([[REG1]])
+; LARGE: lwz {{[0-9]+}}, 0([[REG2]])
+; LARGE: stw {{[0-9]+}}, 0([[REG2]])
+; LARGE: .type [[VAR]], at object
+; LARGE: .data
+; LARGE: .globl [[VAR]]
+; LARGE: [[VAR]]:
+; LARGE: .long 5
+
Modified: llvm/trunk/test/CodeGen/PowerPC/mcm-4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/mcm-4.ll?rev=175767&r1=175766&r2=175767&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/mcm-4.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/mcm-4.ll Thu Feb 21 11:12:27 2013
@@ -1,6 +1,7 @@
-; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck -check-prefix=MEDIUM %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck -check-prefix=LARGE %s
-; Test correct code generation for medium code model (32-bit TOC offsets)
+; Test correct code generation for medium and large code model
; for loading a value from the constant pool (TOC-relative).
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
@@ -11,9 +12,16 @@ entry:
ret double 0x3F4FD4920B498CF0
}
-; CHECK: [[VAR:[a-z0-9A-Z_.]+]]:
-; CHECK: .quad 4562098671269285104
-; CHECK: test_double_const:
-; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc at ha
-; CHECK: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc at l
-; CHECK: lfd {{[0-9]+}}, 0([[REG2]])
+; MEDIUM: [[VAR:[a-z0-9A-Z_.]+]]:
+; MEDIUM: .quad 4562098671269285104
+; MEDIUM: test_double_const:
+; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc at ha
+; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc at l
+; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]])
+
+; LARGE: [[VAR:[a-z0-9A-Z_.]+]]:
+; LARGE: .quad 4562098671269285104
+; LARGE: test_double_const:
+; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc at ha
+; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc at l([[REG1]])
+; LARGE: lfd {{[0-9]+}}, 0([[REG2]])
Modified: llvm/trunk/test/CodeGen/PowerPC/mcm-5.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/mcm-5.ll?rev=175767&r1=175766&r2=175767&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/mcm-5.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/mcm-5.ll Thu Feb 21 11:12:27 2013
@@ -1,6 +1,7 @@
; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s
-; Test correct code generation for medium code model (32-bit TOC offsets)
+; Test correct code generation for medium and large code model
; for loading the address of a jump table from the TOC.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
Modified: llvm/trunk/test/CodeGen/PowerPC/mcm-6.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/mcm-6.ll?rev=175767&r1=175766&r2=175767&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/mcm-6.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/mcm-6.ll Thu Feb 21 11:12:27 2013
@@ -1,6 +1,7 @@
; RUN: llc -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s
-; Test correct code generation for medium code model (32-bit TOC offsets)
+; Test correct code generation for medium and large code model
; for loading and storing a tentatively defined variable.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
Modified: llvm/trunk/test/CodeGen/PowerPC/mcm-7.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/mcm-7.ll?rev=175767&r1=175766&r2=175767&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/mcm-7.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/mcm-7.ll Thu Feb 21 11:12:27 2013
@@ -1,6 +1,7 @@
; RUN: llc -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s
-; Test correct code generation for medium code model (32-bit TOC offsets)
+; Test correct code generation for medium and large code model
; for loading a function address.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
Modified: llvm/trunk/test/CodeGen/PowerPC/mcm-8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/mcm-8.ll?rev=175767&r1=175766&r2=175767&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/mcm-8.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/mcm-8.ll Thu Feb 21 11:12:27 2013
@@ -1,6 +1,7 @@
; RUN: llc -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s
-; Test correct code generation for medium code model (32-bit TOC offsets)
+; Test correct code generation for medium and large code model
; for loading a variable with available-externally linkage.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
Modified: llvm/trunk/test/CodeGen/PowerPC/mcm-9.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/mcm-9.ll?rev=175767&r1=175766&r2=175767&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/mcm-9.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/mcm-9.ll Thu Feb 21 11:12:27 2013
@@ -1,6 +1,7 @@
; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s
-; Test correct code generation for medium code model (32-bit TOC offsets)
+; Test correct code generation for medium and large code model
; for loading and storing an aliased external variable.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
Modified: llvm/trunk/test/CodeGen/PowerPC/mcm-obj.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/mcm-obj.ll?rev=175767&r1=175766&r2=175767&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/mcm-obj.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/mcm-obj.ll Thu Feb 21 11:12:27 2013
@@ -1,5 +1,7 @@
; RUN: llc -O0 -mcpu=pwr7 -code-model=medium -filetype=obj %s -o - | \
-; RUN: elf-dump --dump-section-data | FileCheck %s
+; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=MEDIUM %s
+; RUN: llc -O0 -mcpu=pwr7 -code-model=large -filetype=obj %s -o - | \
+; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=LARGE %s
; FIXME: When asm-parse is available, could make this an assembly test.
@@ -19,15 +21,25 @@ entry:
; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
; accessing external variable ei.
;
-; CHECK: '.rela.text'
-; CHECK: Relocation 0
-; CHECK-NEXT: 'r_offset'
-; CHECK-NEXT: 'r_sym', 0x[[SYM1:[0-9]+]]
-; CHECK-NEXT: 'r_type', 0x00000032
-; CHECK: Relocation 1
-; CHECK-NEXT: 'r_offset'
-; CHECK-NEXT: 'r_sym', 0x[[SYM1]]
-; CHECK-NEXT: 'r_type', 0x00000040
+; MEDIUM: '.rela.text'
+; MEDIUM: Relocation 0
+; MEDIUM-NEXT: 'r_offset'
+; MEDIUM-NEXT: 'r_sym', 0x[[SYM1:[0-9]+]]
+; MEDIUM-NEXT: 'r_type', 0x00000032
+; MEDIUM: Relocation 1
+; MEDIUM-NEXT: 'r_offset'
+; MEDIUM-NEXT: 'r_sym', 0x[[SYM1]]
+; MEDIUM-NEXT: 'r_type', 0x00000040
+;
+; LARGE: '.rela.text'
+; LARGE: Relocation 0
+; LARGE-NEXT: 'r_offset'
+; LARGE-NEXT: 'r_sym', 0x[[SYM1:[0-9]+]]
+; LARGE-NEXT: 'r_type', 0x00000032
+; LARGE: Relocation 1
+; LARGE-NEXT: 'r_offset'
+; LARGE-NEXT: 'r_sym', 0x[[SYM1]]
+; LARGE-NEXT: 'r_type', 0x00000040
@test_fn_static.si = internal global i32 0, align 4
@@ -42,14 +54,26 @@ entry:
; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
; accessing function-scoped variable si.
;
-; CHECK: Relocation 2
-; CHECK-NEXT: 'r_offset'
-; CHECK-NEXT: 'r_sym', 0x[[SYM2:[0-9]+]]
-; CHECK-NEXT: 'r_type', 0x00000032
-; CHECK: Relocation 3
-; CHECK-NEXT: 'r_offset'
-; CHECK-NEXT: 'r_sym', 0x[[SYM2]]
-; CHECK-NEXT: 'r_type', 0x00000030
+; MEDIUM: Relocation 2
+; MEDIUM-NEXT: 'r_offset'
+; MEDIUM-NEXT: 'r_sym', 0x[[SYM2:[0-9]+]]
+; MEDIUM-NEXT: 'r_type', 0x00000032
+; MEDIUM: Relocation 3
+; MEDIUM-NEXT: 'r_offset'
+; MEDIUM-NEXT: 'r_sym', 0x[[SYM2]]
+; MEDIUM-NEXT: 'r_type', 0x00000030
+;
+; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
+; accessing function-scoped variable si.
+;
+; LARGE: Relocation 2
+; LARGE-NEXT: 'r_offset'
+; LARGE-NEXT: 'r_sym', 0x[[SYM2:[0-9]+]]
+; LARGE-NEXT: 'r_type', 0x00000032
+; LARGE: Relocation 3
+; LARGE-NEXT: 'r_offset'
+; LARGE-NEXT: 'r_sym', 0x[[SYM2]]
+; LARGE-NEXT: 'r_type', 0x00000040
@gi = global i32 5, align 4
@@ -64,14 +88,26 @@ entry:
; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
; accessing file-scope variable gi.
;
-; CHECK: Relocation 4
-; CHECK-NEXT: 'r_offset'
-; CHECK-NEXT: 'r_sym', 0x[[SYM3:[0-9]+]]
-; CHECK-NEXT: 'r_type', 0x00000032
-; CHECK: Relocation 5
-; CHECK-NEXT: 'r_offset'
-; CHECK-NEXT: 'r_sym', 0x[[SYM3]]
-; CHECK-NEXT: 'r_type', 0x00000030
+; MEDIUM: Relocation 4
+; MEDIUM-NEXT: 'r_offset'
+; MEDIUM-NEXT: 'r_sym', 0x[[SYM3:[0-9]+]]
+; MEDIUM-NEXT: 'r_type', 0x00000032
+; MEDIUM: Relocation 5
+; MEDIUM-NEXT: 'r_offset'
+; MEDIUM-NEXT: 'r_sym', 0x[[SYM3]]
+; MEDIUM-NEXT: 'r_type', 0x00000030
+;
+; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
+; accessing file-scope variable gi.
+;
+; LARGE: Relocation 4
+; LARGE-NEXT: 'r_offset'
+; LARGE-NEXT: 'r_sym', 0x[[SYM3:[0-9]+]]
+; LARGE-NEXT: 'r_type', 0x00000032
+; LARGE: Relocation 5
+; LARGE-NEXT: 'r_offset'
+; LARGE-NEXT: 'r_sym', 0x[[SYM3]]
+; LARGE-NEXT: 'r_type', 0x00000040
define double @test_double_const() nounwind {
entry:
@@ -81,14 +117,26 @@ entry:
; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
; accessing a constant.
;
-; CHECK: Relocation 6
-; CHECK-NEXT: 'r_offset'
-; CHECK-NEXT: 'r_sym', 0x[[SYM4:[0-9]+]]
-; CHECK-NEXT: 'r_type', 0x00000032
-; CHECK: Relocation 7
-; CHECK-NEXT: 'r_offset'
-; CHECK-NEXT: 'r_sym', 0x[[SYM4]]
-; CHECK-NEXT: 'r_type', 0x00000030
+; MEDIUM: Relocation 6
+; MEDIUM-NEXT: 'r_offset'
+; MEDIUM-NEXT: 'r_sym', 0x[[SYM4:[0-9]+]]
+; MEDIUM-NEXT: 'r_type', 0x00000032
+; MEDIUM: Relocation 7
+; MEDIUM-NEXT: 'r_offset'
+; MEDIUM-NEXT: 'r_sym', 0x[[SYM4]]
+; MEDIUM-NEXT: 'r_type', 0x00000030
+;
+; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
+; accessing a constant.
+;
+; LARGE: Relocation 6
+; LARGE-NEXT: 'r_offset'
+; LARGE-NEXT: 'r_sym', 0x[[SYM4:[0-9]+]]
+; LARGE-NEXT: 'r_type', 0x00000032
+; LARGE: Relocation 7
+; LARGE-NEXT: 'r_offset'
+; LARGE-NEXT: 'r_sym', 0x[[SYM4]]
+; LARGE-NEXT: 'r_type', 0x00000040
define signext i32 @test_jump_table(i32 signext %i) nounwind {
entry:
@@ -137,14 +185,23 @@ sw.epilog:
; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
; accessing a jump table address.
;
-; CHECK: Relocation 8
-; CHECK-NEXT: 'r_offset'
-; CHECK-NEXT: 'r_sym', 0x[[SYM5:[0-9]+]]
-; CHECK-NEXT: 'r_type', 0x00000032
-; CHECK: Relocation 9
-; CHECK-NEXT: 'r_offset'
-; CHECK-NEXT: 'r_sym', 0x[[SYM5]]
-; CHECK-NEXT: 'r_type', 0x00000040
+; MEDIUM: Relocation 8
+; MEDIUM-NEXT: 'r_offset'
+; MEDIUM-NEXT: 'r_sym', 0x[[SYM5:[0-9]+]]
+; MEDIUM-NEXT: 'r_type', 0x00000032
+; MEDIUM: Relocation 9
+; MEDIUM-NEXT: 'r_offset'
+; MEDIUM-NEXT: 'r_sym', 0x[[SYM5]]
+; MEDIUM-NEXT: 'r_type', 0x00000040
+;
+; LARGE: Relocation 8
+; LARGE-NEXT: 'r_offset'
+; LARGE-NEXT: 'r_sym', 0x[[SYM5:[0-9]+]]
+; LARGE-NEXT: 'r_type', 0x00000032
+; LARGE: Relocation 9
+; LARGE-NEXT: 'r_offset'
+; LARGE-NEXT: 'r_sym', 0x[[SYM5]]
+; LARGE-NEXT: 'r_type', 0x00000040
@ti = common global i32 0, align 4
@@ -159,14 +216,23 @@ entry:
; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
; accessing tentatively declared variable ti.
;
-; CHECK: Relocation 10
-; CHECK-NEXT: 'r_offset'
-; CHECK-NEXT: 'r_sym', 0x[[SYM6:[0-9]+]]
-; CHECK-NEXT: 'r_type', 0x00000032
-; CHECK: Relocation 11
-; CHECK-NEXT: 'r_offset'
-; CHECK-NEXT: 'r_sym', 0x[[SYM6]]
-; CHECK-NEXT: 'r_type', 0x00000040
+; MEDIUM: Relocation 10
+; MEDIUM-NEXT: 'r_offset'
+; MEDIUM-NEXT: 'r_sym', 0x[[SYM6:[0-9]+]]
+; MEDIUM-NEXT: 'r_type', 0x00000032
+; MEDIUM: Relocation 11
+; MEDIUM-NEXT: 'r_offset'
+; MEDIUM-NEXT: 'r_sym', 0x[[SYM6]]
+; MEDIUM-NEXT: 'r_type', 0x00000040
+;
+; LARGE: Relocation 10
+; LARGE-NEXT: 'r_offset'
+; LARGE-NEXT: 'r_sym', 0x[[SYM6:[0-9]+]]
+; LARGE-NEXT: 'r_type', 0x00000032
+; LARGE: Relocation 11
+; LARGE-NEXT: 'r_offset'
+; LARGE-NEXT: 'r_sym', 0x[[SYM6]]
+; LARGE-NEXT: 'r_type', 0x00000040
define i8* @test_fnaddr() nounwind {
entry:
@@ -182,12 +248,21 @@ declare signext i32 @foo(i32 signext)
; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
; accessing function address foo.
;
-; CHECK: Relocation 12
-; CHECK-NEXT: 'r_offset'
-; CHECK-NEXT: 'r_sym', 0x[[SYM7:[0-9]+]]
-; CHECK-NEXT: 'r_type', 0x00000032
-; CHECK: Relocation 13
-; CHECK-NEXT: 'r_offset'
-; CHECK-NEXT: 'r_sym', 0x[[SYM7]]
-; CHECK-NEXT: 'r_type', 0x00000040
+; MEDIUM: Relocation 12
+; MEDIUM-NEXT: 'r_offset'
+; MEDIUM-NEXT: 'r_sym', 0x[[SYM7:[0-9]+]]
+; MEDIUM-NEXT: 'r_type', 0x00000032
+; MEDIUM: Relocation 13
+; MEDIUM-NEXT: 'r_offset'
+; MEDIUM-NEXT: 'r_sym', 0x[[SYM7]]
+; MEDIUM-NEXT: 'r_type', 0x00000040
+;
+; LARGE: Relocation 12
+; LARGE-NEXT: 'r_offset'
+; LARGE-NEXT: 'r_sym', 0x[[SYM7:[0-9]+]]
+; LARGE-NEXT: 'r_type', 0x00000032
+; LARGE: Relocation 13
+; LARGE-NEXT: 'r_offset'
+; LARGE-NEXT: 'r_sym', 0x[[SYM7]]
+; LARGE-NEXT: 'r_type', 0x00000040
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