[llvm] r175733 - R600/SI: Make sure M0 is loaded for V_INTERP_MOV_F32

[Michel Danzer]

Author: daenzer
Date: Thu Feb 21 02:57:10 2013
New Revision: 175733

URL: http://llvm.org/viewvc/llvm-project?rev=175733&view=rev
Log:
R600/SI: Make sure M0 is loaded for V_INTERP_MOV_F32

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>

Added:
    llvm/trunk/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll
Modified:
    llvm/trunk/lib/Target/R600/SIInstructions.td

Modified: llvm/trunk/lib/Target/R600/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstructions.td?rev=175733&r1=175732&r2=175733&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/R600/SIInstructions.td Thu Feb 21 02:57:10 2013
@@ -1311,7 +1311,8 @@ def : Pat <
 
 def : Pat <
   (int_SI_fs_interp_constant imm:$attr_chan, imm:$attr, SReg_32:$params),
-  (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, SReg_32:$params)
+  (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr,
+                    (S_MOV_B32 SReg_32:$params))
 >;
 
 def : Pat <

Added: llvm/trunk/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll?rev=175733&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll (added)
+++ llvm/trunk/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll Thu Feb 21 02:57:10 2013
@@ -0,0 +1,23 @@
+;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
+
+;CHECK: S_MOV_B32
+;CHECK-NEXT: V_INTERP_MOV_F32
+
+define void @main() {
+main_body:
+  call void @llvm.AMDGPU.shader.type(i32 0)
+  %0 = load i32 addrspace(8)* inttoptr (i32 6 to i32 addrspace(8)*)
+  %1 = call float @llvm.SI.fs.interp.constant(i32 0, i32 0, i32 %0)
+  %2 = call i32 @llvm.SI.packf16(float %1, float %1)
+  %3 = bitcast i32 %2 to float
+  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3)
+  ret void
+}
+
+declare void @llvm.AMDGPU.shader.type(i32)
+
+declare float @llvm.SI.fs.interp.constant(i32, i32, i32) readonly
+
+declare i32 @llvm.SI.packf16(float, float) readnone
+
+declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)