[PATCH] Add HLE target feature

[Michael Liao]

Hi Nadav

HLE is different from regular transactional memory which requires new
primitive being used by developers. HLE distinguishs that by adding hint
into existing atomic builtins (__atomic__* builtins) which are used to
implement mutex, lock, and other synchronization primitives. All these
atomic builtins are inlined and generated by LLVM backend. With the
extra HLE hint (XACQ/XREL), the processor treats the previous critical
section as a transactional section, abort it if conflicts or commit it
once XREL hint is found without conflicts. The series of patches is to
enable code generation HLE-hinted atomic builtins. Let me whether it
justifies the motivation of adding them into LLVM.

Thanks
- Michael

On Wed, 2013-02-20 at 14:22 -0800, Nadav Rotem wrote:
> Hi Michael, 
> 
> I wrote you yesterday but you may have missed my email. Why do you want to add transactional memory support to LLVM ?  Can't you implement transactional memory using a library call ?  Judging by the number of patches it looks like a major change to LLVM, and I am not sure that I understand the motivation for including it in LLVM.  
> 
> Thanks,
> Nadav
> 
> 
> On Feb 20, 2013, at 2:17 PM, darkbuck <michael.hliao at gmail.com> wrote:
> 
> > Hi nadav,
> > 
> > Add 'FeatureHLE' and auto-detection support
> > 
> > http://llvm-reviews.chandlerc.com/D437
> > 
> > Files:
> >  lib/Target/X86/X86.td
> >  lib/Target/X86/X86InstrInfo.td
> >  lib/Target/X86/X86Subtarget.cpp
> >  lib/Target/X86/X86Subtarget.h
> > 
> > Index: lib/Target/X86/X86.td
> > ===================================================================
> > --- lib/Target/X86/X86.td
> > +++ lib/Target/X86/X86.td
> > @@ -120,6 +120,8 @@
> >                                       "Support BMI2 instructions">;
> > def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
> >                                       "Support RTM instructions">;
> > +def FeatureHLE     : SubtargetFeature<"hle", "HasHLE", "true",
> > +                                      "Support HLE">;
> > def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
> >                                       "Support ADX instructions">;
> > def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
> > @@ -201,7 +203,7 @@
> >                                FeatureRDRAND, FeatureF16C, FeatureFSGSBase,
> >                                FeatureMOVBE, FeatureLZCNT, FeatureBMI,
> >                                FeatureBMI2, FeatureFMA,
> > -                               FeatureRTM]>;
> > +                               FeatureRTM, FeatureHLE]>;
> > 
> > def : Proc<"k6",              [FeatureMMX]>;
> > def : Proc<"k6-2",            [Feature3DNow]>;
> > Index: lib/Target/X86/X86InstrInfo.td
> > ===================================================================
> > --- lib/Target/X86/X86InstrInfo.td
> > +++ lib/Target/X86/X86InstrInfo.td
> > @@ -603,6 +603,7 @@
> > def HasBMI       : Predicate<"Subtarget->hasBMI()">;
> > def HasBMI2      : Predicate<"Subtarget->hasBMI2()">;
> > def HasRTM       : Predicate<"Subtarget->hasRTM()">;
> > +def HasHLE       : Predicate<"Subtarget->hasHLE()">;
> > def HasADX       : Predicate<"Subtarget->hasADX()">;
> > def FPStackf32   : Predicate<"!Subtarget->hasSSE1()">;
> > def FPStackf64   : Predicate<"!Subtarget->hasSSE2()">;
> > Index: lib/Target/X86/X86Subtarget.cpp
> > ===================================================================
> > --- lib/Target/X86/X86Subtarget.cpp
> > +++ lib/Target/X86/X86Subtarget.cpp
> > @@ -310,6 +310,10 @@
> >         HasBMI = true;
> >         ToggleFeature(X86::FeatureBMI);
> >       }
> > +      if ((EBX >> 4) & 0x1) {
> > +        HasHLE = true;
> > +        ToggleFeature(X86::FeatureHLE);
> > +      }
> >       if (IsIntel && ((EBX >> 5) & 0x1)) {
> >         X86SSELevel = AVX2;
> >         ToggleFeature(X86::FeatureAVX2);
> > @@ -439,6 +443,7 @@
> >   HasBMI = false;
> >   HasBMI2 = false;
> >   HasRTM = false;
> > +  HasHLE = false;
> >   HasADX = false;
> >   IsBTMemSlow = false;
> >   IsUAMemFast = false;
> > Index: lib/Target/X86/X86Subtarget.h
> > ===================================================================
> > --- lib/Target/X86/X86Subtarget.h
> > +++ lib/Target/X86/X86Subtarget.h
> > @@ -121,6 +121,9 @@
> >   /// HasRTM - Processor has RTM instructions.
> >   bool HasRTM;
> > 
> > +  /// HasHLE - Processor has HLE.
> > +  bool HasHLE;
> > +
> >   /// HasADX - Processor has ADX instructions.
> >   bool HasADX;
> > 
> > @@ -253,6 +256,7 @@
> >   bool hasBMI() const { return HasBMI; }
> >   bool hasBMI2() const { return HasBMI2; }
> >   bool hasRTM() const { return HasRTM; }
> > +  bool hasHLE() const { return HasHLE; }
> >   bool hasADX() const { return HasADX; }
> >   bool isBTMemSlow() const { return IsBTMemSlow; }
> >   bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
> > <D437.1.patch>_______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
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