[PATCH] Fix PR15267

[Michael Liao]

Thanks for review. Test case is revised following your suggestion plus
one minor fix in the logic, when we load bytes, we only need
any-extload, which is irrelevant to the extload type in the original
vector load.

Thanks
- Michael

On Tue, 2013-02-19 at 23:05 -0800, Nadav Rotem wrote:
> Michael, 
> 
> Your test case does not check the mechanism that you described.  Please write a test case that checks that there is a sequence of shifts and ands. 
> 
> Thanks,
> Nadav
> 
> On Feb 19, 2013, at 10:29 PM, Michael Liao <michael.liao at intel.com> wrote:
> 
> > Hi All,
> > 
> > The root cause of PR15267 is the current logic assume byte-addressable
> > element during extloading from a vector. With <4 x i1> in memory, this
> > logic breaks. The attached patch fixes that by loading all bytes
> > associated to that type, extracting bits and re-packing them again to
> > form each element.
> > 
> > Thanks for review!
> > - Michael
> > 
> > <0001-Fix-PR15267.patch>_______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 

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