[llvm] r175516 - R600: Fix tracking of implicit defs in the IndirectAddressing pass

[Tom Stellard]

Author: tstellar
Date: Tue Feb 19 09:22:42 2013
New Revision: 175516

URL: http://llvm.org/viewvc/llvm-project?rev=175516&view=rev
Log:
R600: Fix tracking of implicit defs in the IndirectAddressing pass

In some cases, we were losing track of live implicit registers which
was creating dead defs and causing the scheduler to produce invalid
code.

NOTE: This is a candidate for the Mesa stable branch.

Modified:
    llvm/trunk/lib/Target/R600/AMDGPUIndirectAddressing.cpp

Modified: llvm/trunk/lib/Target/R600/AMDGPUIndirectAddressing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUIndirectAddressing.cpp?rev=175516&r1=175515&r2=175516&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/AMDGPUIndirectAddressing.cpp (original)
+++ llvm/trunk/lib/Target/R600/AMDGPUIndirectAddressing.cpp Tue Feb 19 09:22:42 2013
@@ -169,9 +169,6 @@ bool AMDGPUIndirectAddressingPass::runOn
         }
 
         if (RegisterAddressMap[Reg] == Address) {
-          if (!regHasExplicitDef(MRI, Reg)) {
-            continue;
-          }
           PhiRegisters.push_back(Reg);
         }
       }
@@ -270,7 +267,8 @@ bool AMDGPUIndirectAddressingPass::runOn
           // instruction that uses indirect addressing. 
           BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDGPU::COPY),
                    MI.getOperand(0).getReg())
-                   .addReg(AddrReg);
+                   .addReg(AddrReg)
+                   .addReg(Reg, RegState::Implicit);
         }
       } else {
         // Indirect register access
@@ -292,8 +290,7 @@ bool AMDGPUIndirectAddressingPass::runOn
           // We only need to use REG_SEQUENCE for explicit defs, since the
           // register coalescer won't do anything with the implicit defs.
           MachineInstr *DefInstr = MRI.getVRegDef(Reg);
-          if (!DefInstr->getOperand(0).isReg() ||
-              DefInstr->getOperand(0).getReg() != Reg) {
+          if (!regHasExplicitDef(MRI, Reg)) {
             continue;
           }
 
@@ -310,6 +307,7 @@ bool AMDGPUIndirectAddressingPass::runOn
 
 
         Mov.addReg(IndirectReg, RegState::Implicit | RegState::Kill);
+        Mov.addReg(LiveAddressRegisterMap[Address], RegState::Implicit);
 
       }
       MI.eraseFromParent();
@@ -321,6 +319,26 @@ bool AMDGPUIndirectAddressingPass::runOn
 bool AMDGPUIndirectAddressingPass::regHasExplicitDef(MachineRegisterInfo &MRI,
                                                   unsigned Reg) const {
   MachineInstr *DefInstr = MRI.getVRegDef(Reg);
-  return DefInstr && DefInstr->getOperand(0).isReg() &&
+
+  if (!DefInstr) {
+    return false;
+  }
+
+  if (DefInstr->getOpcode() == AMDGPU::PHI) {
+    bool Explicit = false;
+    for (MachineInstr::const_mop_iterator I = DefInstr->operands_begin(),
+                                          E = DefInstr->operands_end();
+                                          I != E; ++I) {
+      const MachineOperand &MO = *I;
+      if (!MO.isReg() || MO.isDef()) {
+        continue;
+      }
+
+      Explicit = Explicit || regHasExplicitDef(MRI, MO.getReg());
+    }
+    return Explicit;
+  }
+
+  return DefInstr->getOperand(0).isReg() &&
          DefInstr->getOperand(0).getReg() == Reg;
 }