[llvm] r175419 - Expand pseudo/macro BteqzT8SltuX16 . There is no test case because

[Reed Kotler]

Author: rkotler
Date: Sun Feb 17 22:55:38 2013
New Revision: 175419

URL: http://llvm.org/viewvc/llvm-project?rev=175419&view=rev
Log:
Expand pseudo/macro BteqzT8SltuX16 . There is no test case because
at this time, llvm is generating a different but equivalent pattern
that would lead to this instruction. I am trying to think of a way
to get it to generate this. If I can't, I may just remove the pseudo.


Modified:
    llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp
    llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp?rev=175419&r1=175418&r2=175419&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp Sun Feb 17 22:55:38 2013
@@ -142,6 +142,11 @@ bool Mips16InstrInfo::expandPostRAPseudo
   case Mips::BteqzT8SltX16:
     ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltRxRy16);
     break;
+  case Mips::BteqzT8SltuX16:
+    // TBD: figure out a way to get this or remove the instruction
+    // altogether.
+    ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltuRxRy16);
+    break;
   case Mips::BtnezT8CmpX16:
     ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::CmpRxRy16);
     break;

Modified: llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td?rev=175419&r1=175418&r2=175419&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td Sun Feb 17 22:55:38 2013
@@ -1012,6 +1012,8 @@ def SltCCRxRy16: FCCRR16_ins<"slt">;
 // Purpose: Set on Less Than Unsigned
 // To record the result of an unsigned less-than comparison.
 //
+def SltuRxRy16: FRR16_ins<0b00011, "sltu", IIAlu>;
+
 def SltuRxRyRz16: FRRTR16_ins<"sltu"> {
   let isCodeGenOnly=1;
 }