[llvm] r175407 - [XCore] Add missing 2r instructions.

[Richard Osborne]

Author: friedgold
Date: Sun Feb 17 16:38:05 2013
New Revision: 175407

URL: http://llvm.org/viewvc/llvm-project?rev=175407&view=rev
Log:
[XCore] Add missing 2r instructions.

These instructions are not targeted by the compiler but it is needed for
the MC layer.

Modified:
    llvm/trunk/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
    llvm/trunk/lib/Target/XCore/XCoreInstrFormats.td
    llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td
    llvm/trunk/test/MC/Disassembler/XCore/xcore.txt

Modified: llvm/trunk/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp?rev=175407&r1=175406&r2=175407&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp Sun Feb 17 16:38:05 2013
@@ -100,6 +100,11 @@ static DecodeStatus Decode2RInstruction(
                                         uint64_t Address,
                                         const void *Decoder);
 
+static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
+                                           unsigned Insn,
+                                           uint64_t Address,
+                                           const void *Decoder);
+
 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
                                          unsigned Insn,
                                          uint64_t Address,
@@ -343,6 +348,19 @@ Decode2RInstruction(MCInst &Inst, unsign
   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
   return S;
 }
+
+static DecodeStatus
+Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
+                       const void *Decoder) {
+  unsigned Op1, Op2;
+  DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
+  if (S != MCDisassembler::Success)
+    return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+  Inst.addOperand(MCOperand::CreateImm(Op1));
+  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+  return S;
+}
 
 static DecodeStatus
 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,

Modified: llvm/trunk/lib/Target/XCore/XCoreInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrFormats.td?rev=175407&r1=175406&r2=175407&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreInstrFormats.td (original)
+++ llvm/trunk/lib/Target/XCore/XCoreInstrFormats.td Sun Feb 17 16:38:05 2013
@@ -158,6 +158,14 @@ class _F2R<bits<6> opc, dag outs, dag in
   let DecoderMethod = "Decode2RInstruction";
 }
 
+// 2R with first operand as an immediate. Used for TSETMR where the first
+// operand is treated as an immediate since it refers to a register number in
+// another thread.
+class _F2RImm<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
+    : _F2R<opc, outs, ins, asmstr, pattern> {
+  let DecoderMethod = "Decode2RImmInstruction";
+}
+
 // 2R with first operand as both a source and a destination.
 class _F2RSrcDst<bits<6> opc, dag outs, dag ins, string asmstr,
                  list<dag> pattern> : _F2R<opc, outs, ins, asmstr, pattern> {

Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td?rev=175407&r1=175406&r2=175407&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td (original)
+++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Sun Feb 17 16:38:05 2013
@@ -700,7 +700,6 @@ def LDWCP_lu10 : _FLU10<0b111001, (outs)
 }
 
 // Two operand short
-// TODO eet, eef, tsetmr
 def NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b),
                 "not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>;
 
@@ -848,6 +847,15 @@ def ENDIN_2r : _F2R<0b100101, (outs GRRe
                      "endin $dst, res[$src]",
                      [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>;
 
+def EEF_2r : _F2R<0b001011, (outs), (ins GRRegs:$a, GRRegs:$b),
+                  "eef $a, res[$b]", []>;
+
+def EET_2r : _F2R<0b001001, (outs), (ins GRRegs:$a, GRRegs:$b),
+                  "eet $a, res[$b]", []>;
+
+def TSETMR_2r : _F2RImm<0b000111, (outs), (ins i32imm:$a, GRRegs:$b),
+                        "tsetmr r$a, $b", []>;
+
 // Two operand long
 def BITREV_l2r : _FL2R<0b0000011000, (outs GRRegs:$dst), (ins GRRegs:$src),
                        "bitrev $dst, $src",

Modified: llvm/trunk/test/MC/Disassembler/XCore/xcore.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/XCore/xcore.txt?rev=175407&r1=175406&r2=175407&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/XCore/xcore.txt (original)
+++ llvm/trunk/test/MC/Disassembler/XCore/xcore.txt Sun Feb 17 16:38:05 2013
@@ -217,6 +217,15 @@
 # CHECK: sext r9, r1
 0x45 0x37
 
+# CHECK: tsetmr r7, r3
+0x1f 0x1f
+
+# CHECK: eef r1, res[r6]
+0x96 0x2f
+
+# CHECK: eet r11, res[r0]
+0x5c 0x27
+
 # rus instructions
 
 # CHECK: chkct res[r1], 8