[llvm] r175300 - [mips] Split SelectAddr, which was used to match address patterns, into two
Akira Hatanaka
ahatanaka at mips.com
Fri Feb 15 13:20:45 PST 2013
Author: ahatanak
Date: Fri Feb 15 15:20:45 2013
New Revision: 175300
URL: http://llvm.org/viewvc/llvm-project?rev=175300&view=rev
Log:
[mips] Split SelectAddr, which was used to match address patterns, into two
functions. Set AddedComplexity to determine the order in which patterns are
matched.
This simplifies selection of floating point loads/stores.
No functionality change intended.
Modified:
llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=175300&r1=175299&r2=175300&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Fri Feb 15 15:20:45 2013
@@ -96,7 +96,17 @@ private:
SDNode *Select(SDNode *N);
// Complex Pattern.
- bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Offset);
+ /// (reg + imm).
+ bool selectAddrRegImm(SDNode *Parent, SDValue Addr, SDValue &Base,
+ SDValue &Offset) const;
+
+ /// Fall back on this function if all else fails.
+ bool selectAddrDefault(SDNode *Parent, SDValue Addr, SDValue &Base,
+ SDValue &Offset) const;
+
+ /// Match integer address pattern.
+ bool selectIntAddr(SDNode *Parent, SDValue Addr, SDValue &Base,
+ SDValue &Offset) const;
bool SelectAddr16(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Offset,
SDValue &Alias);
@@ -323,8 +333,8 @@ SDValue MipsDAGToDAGISel::getMips16SPAli
/// ComplexPattern used on MipsInstrInfo
/// Used on Mips Load/Store instructions
-bool MipsDAGToDAGISel::
-SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) {
+bool MipsDAGToDAGISel::selectAddrRegImm(SDNode *Parent, SDValue Addr,
+ SDValue &Base, SDValue &Offset) const {
EVT ValTy = Addr.getValueType();
// if Address is FI, get the TargetFrameIndex.
@@ -384,21 +394,24 @@ SelectAddr(SDNode *Parent, SDValue Addr,
return true;
}
}
-
- // If an indexed floating point load/store can be emitted, return false.
- const LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(Parent);
-
- if (LS &&
- (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
- Subtarget.hasFPIdx())
- return false;
}
- Base = Addr;
- Offset = CurDAG->getTargetConstant(0, ValTy);
+ return false;
+}
+
+bool MipsDAGToDAGISel::selectAddrDefault(SDNode *Parent, SDValue Addr,
+ SDValue &Base, SDValue &Offset) const {
+ Base = Addr;
+ Offset = CurDAG->getTargetConstant(0, Addr.getValueType());
return true;
}
+bool MipsDAGToDAGISel::selectIntAddr(SDNode *Parent, SDValue Addr,
+ SDValue &Base, SDValue &Offset) const {
+ return selectAddrRegImm(Parent, Addr, Base, Offset) ||
+ selectAddrDefault(Parent, Addr, Base, Offset);
+}
+
void MipsDAGToDAGISel::getMips16SPRefReg(SDNode *Parent, SDValue &AliasReg) {
SDValue AliasFPReg = CurDAG->getRegister(Mips::S0, TLI.getPointerTy());
if (Parent) {
Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=175300&r1=175299&r2=175300&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Fri Feb 15 15:20:45 2013
@@ -152,14 +152,14 @@ class MTC1_FT_CCR<string opstr, Register
class LW_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
- [(set RC:$rt, (OpNode addr:$addr))], Itin, FrmFI> {
+ [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI> {
let DecoderMethod = "DecodeFMem";
}
class SW_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
- [(OpNode RC:$rt, addr:$addr)], Itin, FrmFI> {
+ [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI> {
let DecoderMethod = "DecodeFMem";
}
@@ -180,13 +180,17 @@ class LWXC1_FT<string opstr, RegisterCla
InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
InstSE<(outs DRC:$fd), (ins PRC:$base, PRC:$index),
!strconcat(opstr, "\t$fd, ${index}(${base})"),
- [(set DRC:$fd, (OpNode (add PRC:$base, PRC:$index)))], Itin, FrmFI>;
+ [(set DRC:$fd, (OpNode (add PRC:$base, PRC:$index)))], Itin, FrmFI> {
+ let AddedComplexity = 20;
+}
class SWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC,
InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
InstSE<(outs), (ins DRC:$fs, PRC:$base, PRC:$index),
!strconcat(opstr, "\t$fs, ${index}(${base})"),
- [(OpNode DRC:$fs, (add PRC:$base, PRC:$index))], Itin, FrmFI>;
+ [(OpNode DRC:$fs, (add PRC:$base, PRC:$index))], Itin, FrmFI> {
+ let AddedComplexity = 20;
+}
class BC1F_FT<string opstr, InstrItinClass Itin,
SDPatternOperator Op = null_frag> :
@@ -498,3 +502,33 @@ let Predicates = [IsFP64bit, HasStdEnc]
def : MipsPat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>;
def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>;
}
+
+// Load/Store patterns.
+let AddedComplexity = 40 in {
+ let Predicates = [IsN64, HasStdEnc] in {
+ def : MipsPat<(f32 (load addrRegImm:$a)), (LWC1_P8 addrRegImm:$a)>;
+ def : MipsPat<(store FGR32:$v, addrRegImm:$a),
+ (SWC1_P8 FGR32:$v, addrRegImm:$a)>;
+ def : MipsPat<(f64 (load addrRegImm:$a)), (LDC164_P8 addrRegImm:$a)>;
+ def : MipsPat<(store FGR64:$v, addrRegImm:$a),
+ (SDC164_P8 FGR64:$v, addrRegImm:$a)>;
+ }
+
+ let Predicates = [NotN64, HasStdEnc] in {
+ def : MipsPat<(f32 (load addrRegImm:$a)), (LWC1 addrRegImm:$a)>;
+ def : MipsPat<(store FGR32:$v, addrRegImm:$a),
+ (SWC1 FGR32:$v, addrRegImm:$a)>;
+ }
+
+ let Predicates = [NotN64, HasMips64, HasStdEnc] in {
+ def : MipsPat<(f64 (load addrRegImm:$a)), (LDC164 addrRegImm:$a)>;
+ def : MipsPat<(store FGR64:$v, addrRegImm:$a),
+ (SDC164 FGR64:$v, addrRegImm:$a)>;
+ }
+
+ let Predicates = [NotN64, NotMips64, HasStdEnc] in {
+ def : MipsPat<(f64 (load addrRegImm:$a)), (LDC1 addrRegImm:$a)>;
+ def : MipsPat<(store AFGR64:$v, addrRegImm:$a),
+ (SDC1 AFGR64:$v, addrRegImm:$a)>;
+ }
+}
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=175300&r1=175299&r2=175300&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Fri Feb 15 15:20:45 2013
@@ -334,7 +334,13 @@ def immZExt5 : ImmLeaf<i32, [{return Imm
// Mips Address Mode! SDNode frameindex could possibily be a match
// since load and store instructions from stack used it.
def addr :
- ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
+ ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex], [SDNPWantParent]>;
+
+def addrRegImm :
+ ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex], [SDNPWantParent]>;
+
+def addrDefault :
+ ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex], [SDNPWantParent]>;
//===----------------------------------------------------------------------===//
// Instructions specific format
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