[llvm] r175258 - AArch64: remove ConstantIsland pass & put literals in separate section.
Tim Northover
Tim.Northover at arm.com
Fri Feb 15 01:33:44 PST 2013
Author: tnorthover
Date: Fri Feb 15 03:33:43 2013
New Revision: 175258
URL: http://llvm.org/viewvc/llvm-project?rev=175258&view=rev
Log:
AArch64: remove ConstantIsland pass & put literals in separate section.
This implements the review suggestion to simplify the AArch64 backend. If we
later discover that we *really* need the extra complexity of the
ConstantIslands pass for performance reasons it can be resurrected.
Removed:
llvm/trunk/lib/Target/AArch64/AArch64ConstantIslandPass.cpp
Modified:
llvm/trunk/lib/Target/AArch64/AArch64.h
llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.h
llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
llvm/trunk/lib/Target/AArch64/AArch64MachineFunctionInfo.h
llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp
llvm/trunk/lib/Target/AArch64/CMakeLists.txt
llvm/trunk/test/CodeGen/AArch64/adrp-relocation.ll
llvm/trunk/test/CodeGen/AArch64/extern-weak.ll
llvm/trunk/test/CodeGen/AArch64/fp-cond-sel.ll
llvm/trunk/test/CodeGen/AArch64/fp128-folding.ll
llvm/trunk/test/CodeGen/AArch64/fp128.ll
llvm/trunk/test/CodeGen/AArch64/fpimm.ll
llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll
llvm/trunk/test/CodeGen/AArch64/func-calls.ll
llvm/trunk/test/CodeGen/AArch64/literal_pools.ll
Modified: llvm/trunk/lib/Target/AArch64/AArch64.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.h?rev=175258&r1=175257&r2=175258&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64.h Fri Feb 15 03:33:43 2013
@@ -29,8 +29,6 @@ class MCInst;
FunctionPass *createAArch64ISelDAG(AArch64TargetMachine &TM,
CodeGenOpt::Level OptLevel);
-FunctionPass *createAArch64ConstantIslandPass();
-
FunctionPass *createAArch64CleanupLocalDynamicTLSPass();
void LowerAArch64MachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
Modified: llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp?rev=175258&r1=175257&r2=175258&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp Fri Feb 15 03:33:43 2013
@@ -17,7 +17,6 @@
#include "InstPrinter/AArch64InstPrinter.h"
#include "llvm/DebugInfo.h"
#include "llvm/ADT/SmallString.h"
-#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineModuleInfoImpls.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/MC/MCAsmInfo.h"
@@ -298,20 +297,6 @@ void AArch64AsmPrinter::EmitInstruction(
return;
switch (MI->getOpcode()) {
- case AArch64::CONSTPOOL_ENTRY: {
- unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
- unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
-
- OutStreamer.EmitLabel(GetCPISymbol(LabelId));
-
- const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
- if (MCPE.isMachineConstantPoolEntry())
- EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
- else
- EmitGlobalConstant(MCPE.Val.ConstVal);
-
- return;
- }
case AArch64::DBG_VALUE: {
if (isVerbose() && OutStreamer.hasRawTextSupport()) {
SmallString<128> TmpStr;
@@ -352,7 +337,6 @@ void AArch64AsmPrinter::EmitEndOfAsmFile
}
bool AArch64AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
- MCP = MF.getConstantPool();
return AsmPrinter::runOnMachineFunction(MF);
}
Modified: llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.h?rev=175258&r1=175257&r2=175258&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.h Fri Feb 15 03:33:43 2013
@@ -29,7 +29,6 @@ class LLVM_LIBRARY_VISIBILITY AArch64Asm
/// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
/// make the right decision when printing asm code for different targets.
const AArch64Subtarget *Subtarget;
- const MachineConstantPool *MCP;
// emitPseudoExpansionLowering - tblgen'erated.
bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
@@ -74,10 +73,6 @@ class LLVM_LIBRARY_VISIBILITY AArch64Asm
return "AArch64 Assembly Printer";
}
- /// A no-op on AArch64 because we emit our constant pool entries inline with
- /// the function.
- virtual void EmitConstantPool() {}
-
virtual bool runOnMachineFunction(MachineFunction &MF);
};
} // end namespace llvm
Removed: llvm/trunk/lib/Target/AArch64/AArch64ConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ConstantIslandPass.cpp?rev=175257&view=auto
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ConstantIslandPass.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ConstantIslandPass.cpp (removed)
@@ -1,1423 +0,0 @@
-//===-- AArch64ConstantIslandPass.cpp - AArch64 constant islands ----------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains a pass that splits the constant pool up into 'islands'
-// which are scattered through-out the function. This is required due to the
-// limited pc-relative displacements that AArch64 has.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "aarch64-cp-islands"
-#include "AArch64.h"
-#include "AArch64InstrInfo.h"
-#include "AArch64MachineFunctionInfo.h"
-#include "AArch64Subtarget.h"
-#include "AArch64MachineFunctionInfo.h"
-#include "Utils/AArch64BaseInfo.h"
-#include "llvm/CodeGen/MachineConstantPool.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineJumpTableInfo.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/IR/DataLayout.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/Format.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/ADT/SmallSet.h"
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/STLExtras.h"
-#include "llvm/ADT/Statistic.h"
-#include "llvm/Support/CommandLine.h"
-#include <algorithm>
-using namespace llvm;
-
-STATISTIC(NumCPEs, "Number of constpool entries");
-STATISTIC(NumSplit, "Number of uncond branches inserted");
-STATISTIC(NumCBrFixed, "Number of cond branches fixed");
-
-// FIXME: This option should be removed once it has received sufficient testing.
-static cl::opt<bool>
-AlignConstantIslands("aarch64-align-constant-islands", cl::Hidden,
- cl::init(true),
- cl::desc("Align constant islands in code"));
-
-/// Return the worst case padding that could result from unknown offset bits.
-/// This does not include alignment padding caused by known offset bits.
-///
-/// @param LogAlign log2(alignment)
-/// @param KnownBits Number of known low offset bits.
-static inline unsigned UnknownPadding(unsigned LogAlign, unsigned KnownBits) {
- if (KnownBits < LogAlign)
- return (1u << LogAlign) - (1u << KnownBits);
- return 0;
-}
-
-namespace {
- /// Due to limited PC-relative displacements, AArch64 requires constant pool
- /// entries to be scattered among the instructions inside a function. To do
- /// this, it completely ignores the normal LLVM constant pool; instead, it
- /// places constants wherever it feels like with special instructions.
- ///
- /// The terminology used in this pass includes:
- /// Islands - Clumps of constants placed in the function.
- /// Water - Potential places where an island could be formed.
- /// CPE - A constant pool entry that has been placed somewhere, which
- /// tracks a list of users.
- class AArch64ConstantIslands : public MachineFunctionPass {
- /// Information about the offset and size of a single basic block.
- struct BasicBlockInfo {
- /// Distance from the beginning of the function to the beginning of this
- /// basic block.
- ///
- /// Offsets are computed assuming worst case padding before an aligned
- /// block. This means that subtracting basic block offsets always gives a
- /// conservative estimate of the real distance which may be smaller.
- ///
- /// Because worst case padding is used, the computed offset of an aligned
- /// block may not actually be aligned.
- unsigned Offset;
-
- /// Size of the basic block in bytes. If the block contains inline
- /// assembly, this is a worst case estimate.
- ///
- /// The size does not include any alignment padding whether from the
- /// beginning of the block, or from an aligned jump table at the end.
- unsigned Size;
-
- /// The number of low bits in Offset that are known to be exact. The
- /// remaining bits of Offset are an upper bound.
- uint8_t KnownBits;
-
- /// When non-zero, the block contains instructions (inline asm) of unknown
- /// size. The real size may be smaller than Size bytes by a multiple of 1
- /// << Unalign.
- uint8_t Unalign;
-
- BasicBlockInfo() : Offset(0), Size(0), KnownBits(0), Unalign(0) {}
-
- /// Compute the number of known offset bits internally to this block.
- /// This number should be used to predict worst case padding when
- /// splitting the block.
- unsigned internalKnownBits() const {
- unsigned Bits = Unalign ? Unalign : KnownBits;
- // If the block size isn't a multiple of the known bits, assume the
- // worst case padding.
- if (Size & ((1u << Bits) - 1))
- Bits = CountTrailingZeros_32(Size);
- return Bits;
- }
-
- /// Compute the offset immediately following this block. If LogAlign is
- /// specified, return the offset the successor block will get if it has
- /// this alignment.
- unsigned postOffset(unsigned LogAlign = 0) const {
- unsigned PO = Offset + Size;
- if (!LogAlign)
- return PO;
- // Add alignment padding from the terminator.
- return PO + UnknownPadding(LogAlign, internalKnownBits());
- }
-
- /// Compute the number of known low bits of postOffset. If this block
- /// contains inline asm, the number of known bits drops to the
- /// instruction alignment. An aligned terminator may increase the number
- /// of know bits.
- /// If LogAlign is given, also consider the alignment of the next block.
- unsigned postKnownBits(unsigned LogAlign = 0) const {
- return std::max(LogAlign, internalKnownBits());
- }
- };
-
- std::vector<BasicBlockInfo> BBInfo;
-
- /// A sorted list of basic blocks where islands could be placed (i.e. blocks
- /// that don't fall through to the following block, due to a return,
- /// unreachable, or unconditional branch).
- std::vector<MachineBasicBlock*> WaterList;
-
- /// The subset of WaterList that was created since the previous iteration by
- /// inserting unconditional branches.
- SmallSet<MachineBasicBlock*, 4> NewWaterList;
-
- typedef std::vector<MachineBasicBlock*>::iterator water_iterator;
-
- /// One user of a constant pool, keeping the machine instruction pointer,
- /// the constant pool being referenced, and the number of bits used by the
- /// instruction for displacement. The HighWaterMark records the highest
- /// basic block where a new CPEntry can be placed. To ensure this pass
- /// terminates, the CP entries are initially placed at the end of the
- /// function and then move monotonically to lower addresses. The exception
- /// to this rule is when the current CP entry for a particular CPUser is out
- /// of range, but there is another CP entry for the same constant value in
- /// range. We want to use the existing in-range CP entry, but if it later
- /// moves out of range, the search for new water should resume where it left
- /// off. The HighWaterMark is used to record that point.
- struct CPUser {
- MachineInstr *MI;
- MachineInstr *CPEMI;
- MachineBasicBlock *HighWaterMark;
- private:
- unsigned OffsetBits;
- public:
- CPUser(MachineInstr *mi, MachineInstr *cpemi, unsigned offsetbits)
- : MI(mi), CPEMI(cpemi), OffsetBits(offsetbits) {
- HighWaterMark = CPEMI->getParent();
- }
- /// Returns the number of bits used to specify the offset.
- unsigned getOffsetBits() const {
- return OffsetBits;
- }
-
- /// Returns the maximum positive displacement possible from this CPUser
- /// (essentially INT<N>_MAX * 4).
- unsigned getMaxPosDisp() const {
- return (1 << (OffsetBits - 1)) - 1;
- }
- };
-
- /// Keep track of all of the machine instructions that use various constant
- /// pools and their max displacement.
- std::vector<CPUser> CPUsers;
-
- /// One per constant pool entry, keeping the machine instruction pointer,
- /// the constpool index, and the number of CPUser's which reference this
- /// entry.
- struct CPEntry {
- MachineInstr *CPEMI;
- unsigned CPI;
- unsigned RefCount;
- CPEntry(MachineInstr *cpemi, unsigned cpi, unsigned rc = 0)
- : CPEMI(cpemi), CPI(cpi), RefCount(rc) {}
- };
-
- /// Keep track of all of the constant pool entry machine instructions. For
- /// each original constpool index (i.e. those that existed upon entry to
- /// this pass), it keeps a vector of entries. Original elements are cloned
- /// as we go along; the clones are put in the vector of the original
- /// element, but have distinct CPIs.
- std::vector<std::vector<CPEntry> > CPEntries;
-
- /// One per immediate branch, keeping the machine instruction pointer,
- /// conditional or unconditional, the max displacement, and (if IsCond is
- /// true) the corresponding inverted branch opcode.
- struct ImmBranch {
- MachineInstr *MI;
- unsigned OffsetBits : 31;
- bool IsCond : 1;
- ImmBranch(MachineInstr *mi, unsigned offsetbits, bool cond)
- : MI(mi), OffsetBits(offsetbits), IsCond(cond) {}
- };
-
- /// Keep track of all the immediate branch instructions.
- ///
- std::vector<ImmBranch> ImmBranches;
-
- MachineFunction *MF;
- MachineConstantPool *MCP;
- const AArch64InstrInfo *TII;
- const AArch64Subtarget *STI;
- AArch64MachineFunctionInfo *AFI;
- public:
- static char ID;
- AArch64ConstantIslands() : MachineFunctionPass(ID) {}
-
- virtual bool runOnMachineFunction(MachineFunction &MF);
-
- virtual const char *getPassName() const {
- return "AArch64 constant island placement pass";
- }
-
- private:
- void doInitialPlacement(std::vector<MachineInstr*> &CPEMIs);
- CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI);
- unsigned getCPELogAlign(const MachineInstr *CPEMI);
- void scanFunctionJumpTables();
- void initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs);
- MachineBasicBlock *splitBlockBeforeInstr(MachineInstr *MI);
- void updateForInsertedWaterBlock(MachineBasicBlock *NewBB);
- void adjustBBOffsetsAfter(MachineBasicBlock *BB);
- bool decrementCPEReferenceCount(unsigned CPI, MachineInstr* CPEMI);
- int findInRangeCPEntry(CPUser& U, unsigned UserOffset);
- bool findAvailableWater(CPUser&U, unsigned UserOffset,
- water_iterator &WaterIter);
- void createNewWater(unsigned CPUserIndex, unsigned UserOffset,
- MachineBasicBlock *&NewMBB);
- bool handleConstantPoolUser(unsigned CPUserIndex);
- void removeDeadCPEMI(MachineInstr *CPEMI);
- bool removeUnusedCPEntries();
- bool isCPEntryInRange(MachineInstr *MI, unsigned UserOffset,
- MachineInstr *CPEMI, unsigned OffsetBits,
- bool DoDump = false);
- bool isWaterInRange(unsigned UserOffset, MachineBasicBlock *Water,
- CPUser &U, unsigned &Growth);
- bool isBBInRange(MachineInstr *MI, MachineBasicBlock *BB,
- unsigned OffsetBits);
- bool fixupImmediateBr(ImmBranch &Br);
- bool fixupConditionalBr(ImmBranch &Br);
-
- void computeBlockSize(MachineBasicBlock *MBB);
- unsigned getOffsetOf(MachineInstr *MI) const;
- unsigned getUserOffset(CPUser&) const;
- void dumpBBs();
- void verify();
-
- bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
- unsigned BitsAvailable);
- bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
- const CPUser &U) {
- return isOffsetInRange(UserOffset, TrialOffset, U.getOffsetBits());
- }
- };
- char AArch64ConstantIslands::ID = 0;
-}
-
-/// check BBOffsets, BBSizes, alignment of islands
-void AArch64ConstantIslands::verify() {
-#ifndef NDEBUG
- for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
- MBBI != E; ++MBBI) {
- MachineBasicBlock *MBB = MBBI;
- unsigned MBBId = MBB->getNumber();
- assert(!MBBId || BBInfo[MBBId - 1].postOffset() <= BBInfo[MBBId].Offset);
- }
- DEBUG(dbgs() << "Verifying " << CPUsers.size() << " CP users.\n");
- for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
- CPUser &U = CPUsers[i];
- unsigned UserOffset = getUserOffset(U);
- // Verify offset using the real max displacement without the safety
- // adjustment.
- if (isCPEntryInRange(U.MI, UserOffset, U.CPEMI, U.getOffsetBits(),
- /* DoDump = */ true)) {
- DEBUG(dbgs() << "OK\n");
- continue;
- }
- DEBUG(dbgs() << "Out of range.\n");
- dumpBBs();
- DEBUG(MF->dump());
- llvm_unreachable("Constant pool entry out of range!");
- }
-#endif
-}
-
-/// print block size and offset information - debugging
-void AArch64ConstantIslands::dumpBBs() {
- DEBUG({
- for (unsigned J = 0, E = BBInfo.size(); J !=E; ++J) {
- const BasicBlockInfo &BBI = BBInfo[J];
- dbgs() << format("%08x BB#%u\t", BBI.Offset, J)
- << " kb=" << unsigned(BBI.KnownBits)
- << " ua=" << unsigned(BBI.Unalign)
- << format(" size=%#x\n", BBInfo[J].Size);
- }
- });
-}
-
-/// Returns an instance of the constpool island pass.
-FunctionPass *llvm::createAArch64ConstantIslandPass() {
- return new AArch64ConstantIslands();
-}
-
-bool AArch64ConstantIslands::runOnMachineFunction(MachineFunction &mf) {
- MF = &mf;
- MCP = mf.getConstantPool();
-
- DEBUG(dbgs() << "***** AArch64ConstantIslands: "
- << MCP->getConstants().size() << " CP entries, aligned to "
- << MCP->getConstantPoolAlignment() << " bytes *****\n");
-
- TII = (const AArch64InstrInfo*)MF->getTarget().getInstrInfo();
- AFI = MF->getInfo<AArch64MachineFunctionInfo>();
- STI = &MF->getTarget().getSubtarget<AArch64Subtarget>();
-
- // This pass invalidates liveness information when it splits basic blocks.
- MF->getRegInfo().invalidateLiveness();
-
- // Renumber all of the machine basic blocks in the function, guaranteeing that
- // the numbers agree with the position of the block in the function.
- MF->RenumberBlocks();
-
- // Perform the initial placement of the constant pool entries. To start with,
- // we put them all at the end of the function.
- std::vector<MachineInstr*> CPEMIs;
- if (!MCP->isEmpty())
- doInitialPlacement(CPEMIs);
-
- /// The next UID to take is the first unused one.
- AFI->initPICLabelUId(CPEMIs.size());
-
- // Do the initial scan of the function, building up information about the
- // sizes of each block, the location of all the water, and finding all of the
- // constant pool users.
- initializeFunctionInfo(CPEMIs);
- CPEMIs.clear();
- DEBUG(dumpBBs());
-
-
- /// Remove dead constant pool entries.
- bool MadeChange = removeUnusedCPEntries();
-
- // Iteratively place constant pool entries and fix up branches until there
- // is no change.
- unsigned NoCPIters = 0, NoBRIters = 0;
- while (true) {
- DEBUG(dbgs() << "Beginning CP iteration #" << NoCPIters << '\n');
- bool CPChange = false;
- for (unsigned i = 0, e = CPUsers.size(); i != e; ++i)
- CPChange |= handleConstantPoolUser(i);
- if (CPChange && ++NoCPIters > 30)
- report_fatal_error("Constant Island pass failed to converge!");
- DEBUG(dumpBBs());
-
- // Clear NewWaterList now. If we split a block for branches, it should
- // appear as "new water" for the next iteration of constant pool placement.
- NewWaterList.clear();
-
- DEBUG(dbgs() << "Beginning BR iteration #" << NoBRIters << '\n');
- bool BRChange = false;
- for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i)
- BRChange |= fixupImmediateBr(ImmBranches[i]);
- if (BRChange && ++NoBRIters > 30)
- report_fatal_error("Branch Fix Up pass failed to converge!");
- DEBUG(dumpBBs());
-
- if (!CPChange && !BRChange)
- break;
- MadeChange = true;
- }
-
- // After a while, this might be made debug-only, but it is not expensive.
- verify();
-
- DEBUG(dbgs() << '\n'; dumpBBs());
-
- BBInfo.clear();
- WaterList.clear();
- CPUsers.clear();
- CPEntries.clear();
- ImmBranches.clear();
-
- return MadeChange;
-}
-
-/// Perform the initial placement of the constant pool entries. To start with,
-/// we put them all at the end of the function.
-void
-AArch64ConstantIslands::doInitialPlacement(std::vector<MachineInstr*> &CPEMIs) {
- // Create the basic block to hold the CPE's.
- MachineBasicBlock *BB = MF->CreateMachineBasicBlock();
- MF->push_back(BB);
-
- // MachineConstantPool measures alignment in bytes. We measure in log2(bytes).
- unsigned MaxAlign = Log2_32(MCP->getConstantPoolAlignment());
-
- // Mark the basic block as required by the const-pool.
- // If AlignConstantIslands isn't set, use 4-byte alignment for everything.
- BB->setAlignment(AlignConstantIslands ? MaxAlign : 2);
-
- // The function needs to be as aligned as the basic blocks. The linker may
- // move functions around based on their alignment.
- MF->ensureAlignment(BB->getAlignment());
-
- // Order the entries in BB by descending alignment. That ensures correct
- // alignment of all entries as long as BB is sufficiently aligned. Keep
- // track of the insertion point for each alignment. We are going to bucket
- // sort the entries as they are created.
- SmallVector<MachineBasicBlock::iterator, 8> InsPoint(MaxAlign + 1, BB->end());
-
- // Add all of the constants from the constant pool to the end block, use an
- // identity mapping of CPI's to CPE's.
- const std::vector<MachineConstantPoolEntry> &CPs = MCP->getConstants();
-
- const DataLayout &TD = *MF->getTarget().getDataLayout();
- for (unsigned i = 0, e = CPs.size(); i != e; ++i) {
- unsigned Size = TD.getTypeAllocSize(CPs[i].getType());
- assert(Size >= 4 && "Too small constant pool entry");
- unsigned Align = CPs[i].getAlignment();
- assert(isPowerOf2_32(Align) && "Invalid alignment");
- // Verify that all constant pool entries are a multiple of their alignment.
- // If not, we would have to pad them out so that instructions stay aligned.
- assert((Size % Align) == 0 && "CP Entry not multiple of 4 bytes!");
-
- // Insert CONSTPOOL_ENTRY before entries with a smaller alignment.
- unsigned LogAlign = Log2_32(Align);
- MachineBasicBlock::iterator InsAt = InsPoint[LogAlign];
- MachineInstr *CPEMI =
- BuildMI(*BB, InsAt, DebugLoc(), TII->get(AArch64::CONSTPOOL_ENTRY))
- .addImm(i).addConstantPoolIndex(i).addImm(Size);
- CPEMIs.push_back(CPEMI);
-
- // Ensure that future entries with higher alignment get inserted before
- // CPEMI. This is bucket sort with iterators.
- for (unsigned a = LogAlign + 1; a <= MaxAlign; ++a)
- if (InsPoint[a] == InsAt)
- InsPoint[a] = CPEMI;
-
- // Add a new CPEntry, but no corresponding CPUser yet.
- std::vector<CPEntry> CPEs;
- CPEs.push_back(CPEntry(CPEMI, i));
- CPEntries.push_back(CPEs);
- ++NumCPEs;
- DEBUG(dbgs() << "Moved CPI#" << i << " to end of function, size = "
- << Size << ", align = " << Align <<'\n');
- }
- DEBUG(BB->dump());
-}
-
-/// Return true if the specified basic block can fallthrough into the block
-/// immediately after it.
-static bool BBHasFallthrough(MachineBasicBlock *MBB) {
- // Get the next machine basic block in the function.
- MachineFunction::iterator MBBI = MBB;
- // Can't fall off end of function.
- if (llvm::next(MBBI) == MBB->getParent()->end())
- return false;
-
- MachineBasicBlock *NextBB = llvm::next(MBBI);
- for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
- E = MBB->succ_end(); I != E; ++I)
- if (*I == NextBB)
- return true;
-
- return false;
-}
-
-/// Given the constpool index and CONSTPOOL_ENTRY MI, look up the corresponding
-/// CPEntry.
-AArch64ConstantIslands::CPEntry
-*AArch64ConstantIslands::findConstPoolEntry(unsigned CPI,
- const MachineInstr *CPEMI) {
- std::vector<CPEntry> &CPEs = CPEntries[CPI];
- // Number of entries per constpool index should be small, just do a
- // linear search.
- for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
- if (CPEs[i].CPEMI == CPEMI)
- return &CPEs[i];
- }
- return NULL;
-}
-
-/// Returns the required alignment of the constant pool entry represented by
-/// CPEMI. Alignment is measured in log2(bytes) units.
-unsigned AArch64ConstantIslands::getCPELogAlign(const MachineInstr *CPEMI) {
- assert(CPEMI && CPEMI->getOpcode() == AArch64::CONSTPOOL_ENTRY);
-
- // Everything is 4-byte aligned unless AlignConstantIslands is set.
- if (!AlignConstantIslands)
- return 2;
-
- unsigned CPI = CPEMI->getOperand(1).getIndex();
- assert(CPI < MCP->getConstants().size() && "Invalid constant pool index.");
- unsigned Align = MCP->getConstants()[CPI].getAlignment();
- assert(isPowerOf2_32(Align) && "Invalid CPE alignment");
- return Log2_32(Align);
-}
-
-/// Do the initial scan of the function, building up information about the sizes
-/// of each block, the location of all the water, and finding all of the
-/// constant pool users.
-void AArch64ConstantIslands::
-initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
- BBInfo.clear();
- BBInfo.resize(MF->getNumBlockIDs());
-
- // First thing, compute the size of all basic blocks, and see if the function
- // has any inline assembly in it. If so, we have to be conservative about
- // alignment assumptions, as we don't know for sure the size of any
- // instructions in the inline assembly.
- for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I)
- computeBlockSize(I);
-
- // The known bits of the entry block offset are determined by the function
- // alignment.
- BBInfo.front().KnownBits = MF->getAlignment();
-
- // Compute block offsets and known bits.
- adjustBBOffsetsAfter(MF->begin());
-
- // Now go back through the instructions and build up our data structures.
- for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
- MBBI != E; ++MBBI) {
- MachineBasicBlock &MBB = *MBBI;
-
- // If this block doesn't fall through into the next MBB, then this is
- // 'water' that a constant pool island could be placed.
- if (!BBHasFallthrough(&MBB))
- WaterList.push_back(&MBB);
-
- for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
- I != E; ++I) {
- if (I->isDebugValue())
- continue;
-
- int Opc = I->getOpcode();
- if (I->isBranch()) {
- bool IsCond = false;
-
- // The offsets encoded in instructions here scale by the instruction
- // size (4 bytes), effectively increasing their range by 2 bits.
- unsigned Bits = 0;
- switch (Opc) {
- default:
- continue; // Ignore other JT branches
- case AArch64::TBZxii:
- case AArch64::TBZwii:
- case AArch64::TBNZxii:
- case AArch64::TBNZwii:
- IsCond = true;
- Bits = 14 + 2;
- break;
- case AArch64::Bcc:
- case AArch64::CBZx:
- case AArch64::CBZw:
- case AArch64::CBNZx:
- case AArch64::CBNZw:
- IsCond = true;
- Bits = 19 + 2;
- break;
- case AArch64::Bimm:
- Bits = 26 + 2;
- break;
- }
-
- // Record this immediate branch.
- ImmBranches.push_back(ImmBranch(I, Bits, IsCond));
- }
-
- if (Opc == AArch64::CONSTPOOL_ENTRY)
- continue;
-
- // Scan the instructions for constant pool operands.
- for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op)
- if (I->getOperand(op).isCPI()) {
- // We found one. The addressing mode tells us the max displacement
- // from the PC that this instruction permits.
-
- // The offsets encoded in instructions here scale by the instruction
- // size (4 bytes), effectively increasing their range by 2 bits.
- unsigned Bits = 0;
-
- switch (Opc) {
- default:
- llvm_unreachable("Unknown addressing mode for CP reference!");
-
- case AArch64::LDRw_lit:
- case AArch64::LDRx_lit:
- case AArch64::LDRs_lit:
- case AArch64::LDRd_lit:
- case AArch64::LDRq_lit:
- case AArch64::LDRSWx_lit:
- case AArch64::PRFM_lit:
- Bits = 19 + 2;
- }
-
- // Remember that this is a user of a CP entry.
- unsigned CPI = I->getOperand(op).getIndex();
- MachineInstr *CPEMI = CPEMIs[CPI];
- CPUsers.push_back(CPUser(I, CPEMI, Bits));
-
- // Increment corresponding CPEntry reference count.
- CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
- assert(CPE && "Cannot find a corresponding CPEntry!");
- CPE->RefCount++;
-
- // Instructions can only use one CP entry, don't bother scanning the
- // rest of the operands.
- break;
- }
- }
- }
-}
-
-/// Compute the size and some alignment information for MBB. This function
-/// updates BBInfo directly.
-void AArch64ConstantIslands::computeBlockSize(MachineBasicBlock *MBB) {
- BasicBlockInfo &BBI = BBInfo[MBB->getNumber()];
- BBI.Size = 0;
- BBI.Unalign = 0;
-
- for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
- ++I) {
- BBI.Size += TII->getInstSizeInBytes(*I);
- // For inline asm, GetInstSizeInBytes returns a conservative estimate.
- // The actual size may be smaller, but still a multiple of the instr size.
- if (I->isInlineAsm())
- BBI.Unalign = 2;
- }
-}
-
-/// Return the current offset of the specified machine instruction from the
-/// start of the function. This offset changes as stuff is moved around inside
-/// the function.
-unsigned AArch64ConstantIslands::getOffsetOf(MachineInstr *MI) const {
- MachineBasicBlock *MBB = MI->getParent();
-
- // The offset is composed of two things: the sum of the sizes of all MBB's
- // before this instruction's block, and the offset from the start of the block
- // it is in.
- unsigned Offset = BBInfo[MBB->getNumber()].Offset;
-
- // Sum instructions before MI in MBB.
- for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) {
- assert(I != MBB->end() && "Didn't find MI in its own basic block?");
- Offset += TII->getInstSizeInBytes(*I);
- }
- return Offset;
-}
-
-/// Little predicate function to sort the WaterList by MBB ID.
-static bool CompareMBBNumbers(const MachineBasicBlock *LHS,
- const MachineBasicBlock *RHS) {
- return LHS->getNumber() < RHS->getNumber();
-}
-
-/// When a block is newly inserted into the machine function, it upsets all of
-/// the block numbers. Renumber the blocks and update the arrays that parallel
-/// this numbering.
-void AArch64ConstantIslands::
-updateForInsertedWaterBlock(MachineBasicBlock *NewBB) {
- // Renumber the MBB's to keep them consecutive.
- NewBB->getParent()->RenumberBlocks(NewBB);
-
- // Insert an entry into BBInfo to align it properly with the (newly
- // renumbered) block numbers.
- BBInfo.insert(BBInfo.begin() + NewBB->getNumber(), BasicBlockInfo());
-
- // Next, update WaterList. Specifically, we need to add NewMBB as having
- // available water after it.
- water_iterator IP =
- std::lower_bound(WaterList.begin(), WaterList.end(), NewBB,
- CompareMBBNumbers);
- WaterList.insert(IP, NewBB);
-}
-
-
-/// Split the basic block containing MI into two blocks, which are joined by
-/// an unconditional branch. Update data structures and renumber blocks to
-/// account for this change and returns the newly created block.
-MachineBasicBlock *
-AArch64ConstantIslands::splitBlockBeforeInstr(MachineInstr *MI) {
- MachineBasicBlock *OrigBB = MI->getParent();
-
- // Create a new MBB for the code after the OrigBB.
- MachineBasicBlock *NewBB =
- MF->CreateMachineBasicBlock(OrigBB->getBasicBlock());
- MachineFunction::iterator MBBI = OrigBB; ++MBBI;
- MF->insert(MBBI, NewBB);
-
- // Splice the instructions starting with MI over to NewBB.
- NewBB->splice(NewBB->end(), OrigBB, MI, OrigBB->end());
-
- // Add an unconditional branch from OrigBB to NewBB.
- // Note the new unconditional branch is not being recorded.
- // There doesn't seem to be meaningful DebugInfo available; this doesn't
- // correspond to anything in the source.
- BuildMI(OrigBB, DebugLoc(), TII->get(AArch64::Bimm)).addMBB(NewBB);
- ++NumSplit;
-
- // Update the CFG. All succs of OrigBB are now succs of NewBB.
- NewBB->transferSuccessors(OrigBB);
-
- // OrigBB branches to NewBB.
- OrigBB->addSuccessor(NewBB);
-
- // Update internal data structures to account for the newly inserted MBB.
- // This is almost the same as updateForInsertedWaterBlock, except that
- // the Water goes after OrigBB, not NewBB.
- MF->RenumberBlocks(NewBB);
-
- // Insert an entry into BBInfo to align it properly with the (newly
- // renumbered) block numbers.
- BBInfo.insert(BBInfo.begin() + NewBB->getNumber(), BasicBlockInfo());
-
- // Next, update WaterList. Specifically, we need to add OrigMBB as having
- // available water after it (but not if it's already there, which happens
- // when splitting before a conditional branch that is followed by an
- // unconditional branch - in that case we want to insert NewBB).
- water_iterator IP =
- std::lower_bound(WaterList.begin(), WaterList.end(), OrigBB,
- CompareMBBNumbers);
- MachineBasicBlock* WaterBB = *IP;
- if (WaterBB == OrigBB)
- WaterList.insert(llvm::next(IP), NewBB);
- else
- WaterList.insert(IP, OrigBB);
- NewWaterList.insert(OrigBB);
-
- // Figure out how large the OrigBB is. As the first half of the original
- // block, it cannot contain a tablejump. The size includes
- // the new jump we added. (It should be possible to do this without
- // recounting everything, but it's very confusing, and this is rarely
- // executed.)
- computeBlockSize(OrigBB);
-
- // Figure out how large the NewMBB is. As the second half of the original
- // block, it may contain a tablejump.
- computeBlockSize(NewBB);
-
- // All BBOffsets following these blocks must be modified.
- adjustBBOffsetsAfter(OrigBB);
-
- return NewBB;
-}
-
-/// Compute the offset of U.MI as seen by the hardware displacement computation.
-unsigned AArch64ConstantIslands::getUserOffset(CPUser &U) const {
- return getOffsetOf(U.MI);
-}
-
-/// Checks whether UserOffset (the location of a constant pool reference) is
-/// within OffsetBits of TrialOffset (a proposed location of a constant pool
-/// entry).
-bool AArch64ConstantIslands::isOffsetInRange(unsigned UserOffset,
- unsigned TrialOffset,
- unsigned OffsetBits) {
- return isIntN(OffsetBits, static_cast<int64_t>(TrialOffset) - UserOffset);
-}
-
-/// Returns true if a CPE placed after the specified Water (a basic block) will
-/// be in range for the specific MI.
-///
-/// Compute how much the function will grow by inserting a CPE after Water.
-bool AArch64ConstantIslands::isWaterInRange(unsigned UserOffset,
- MachineBasicBlock* Water, CPUser &U,
- unsigned &Growth) {
- unsigned CPELogAlign = getCPELogAlign(U.CPEMI);
- unsigned CPEOffset = BBInfo[Water->getNumber()].postOffset(CPELogAlign);
- unsigned NextBlockOffset, NextBlockAlignment;
- MachineFunction::const_iterator NextBlock = Water;
- if (++NextBlock == MF->end()) {
- NextBlockOffset = BBInfo[Water->getNumber()].postOffset();
- NextBlockAlignment = 0;
- } else {
- NextBlockOffset = BBInfo[NextBlock->getNumber()].Offset;
- NextBlockAlignment = NextBlock->getAlignment();
- }
- unsigned Size = U.CPEMI->getOperand(2).getImm();
- unsigned CPEEnd = CPEOffset + Size;
-
- // The CPE may be able to hide in the alignment padding before the next
- // block. It may also cause more padding to be required if it is more aligned
- // that the next block.
- if (CPEEnd > NextBlockOffset) {
- Growth = CPEEnd - NextBlockOffset;
- // Compute the padding that would go at the end of the CPE to align the next
- // block.
- Growth += OffsetToAlignment(CPEEnd, 1u << NextBlockAlignment);
-
- // If the CPE is to be inserted before the instruction, that will raise
- // the offset of the instruction. Also account for unknown alignment padding
- // in blocks between CPE and the user.
- if (CPEOffset < UserOffset)
- UserOffset += Growth + UnknownPadding(MF->getAlignment(), CPELogAlign);
- } else
- // CPE fits in existing padding.
- Growth = 0;
-
- return isOffsetInRange(UserOffset, CPEOffset, U);
-}
-
-/// Returns true if the distance between specific MI and specific ConstPool
-/// entry instruction can fit in MI's displacement field.
-bool AArch64ConstantIslands::isCPEntryInRange(MachineInstr *MI,
- unsigned UserOffset,
- MachineInstr *CPEMI,
- unsigned OffsetBits,
- bool DoDump) {
- unsigned CPEOffset = getOffsetOf(CPEMI);
-
- if (DoDump) {
- DEBUG({
- unsigned Block = MI->getParent()->getNumber();
- const BasicBlockInfo &BBI = BBInfo[Block];
- dbgs() << "User of CPE#" << CPEMI->getOperand(0).getImm()
- << " bits available=" << OffsetBits
- << format(" insn address=%#x", UserOffset)
- << " in BB#" << Block << ": "
- << format("%#x-%x\t", BBI.Offset, BBI.postOffset()) << *MI
- << format("CPE address=%#x offset=%+d: ", CPEOffset,
- int(CPEOffset-UserOffset));
- });
- }
-
- return isOffsetInRange(UserOffset, CPEOffset, OffsetBits);
-}
-
-#ifndef NDEBUG
-/// Return true of the specified basic block's only predecessor unconditionally
-/// branches to its only successor.
-static bool BBIsJumpedOver(MachineBasicBlock *MBB) {
- if (MBB->pred_size() != 1 || MBB->succ_size() != 1)
- return false;
-
- MachineBasicBlock *Succ = *MBB->succ_begin();
- MachineBasicBlock *Pred = *MBB->pred_begin();
- MachineInstr *PredMI = &Pred->back();
- if (PredMI->getOpcode() == AArch64::Bimm)
- return PredMI->getOperand(0).getMBB() == Succ;
- return false;
-}
-#endif // NDEBUG
-
-void AArch64ConstantIslands::adjustBBOffsetsAfter(MachineBasicBlock *BB) {
- unsigned BBNum = BB->getNumber();
- for(unsigned i = BBNum + 1, e = MF->getNumBlockIDs(); i < e; ++i) {
- // Get the offset and known bits at the end of the layout predecessor.
- // Include the alignment of the current block.
- unsigned LogAlign = MF->getBlockNumbered(i)->getAlignment();
- unsigned Offset = BBInfo[i - 1].postOffset(LogAlign);
- unsigned KnownBits = BBInfo[i - 1].postKnownBits(LogAlign);
-
- // This is where block i begins. Stop if the offset is already correct,
- // and we have updated 2 blocks. This is the maximum number of blocks
- // changed before calling this function.
- if (i > BBNum + 2 &&
- BBInfo[i].Offset == Offset &&
- BBInfo[i].KnownBits == KnownBits)
- break;
-
- BBInfo[i].Offset = Offset;
- BBInfo[i].KnownBits = KnownBits;
- }
-}
-
-/// Find the constant pool entry with index CPI and instruction CPEMI, and
-/// decrement its refcount. If the refcount becomes 0 remove the entry and
-/// instruction. Returns true if we removed the entry, false if we didn't.
-bool AArch64ConstantIslands::decrementCPEReferenceCount(unsigned CPI,
- MachineInstr *CPEMI) {
- // Find the old entry. Eliminate it if it is no longer used.
- CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
- assert(CPE && "Unexpected!");
- if (--CPE->RefCount == 0) {
- removeDeadCPEMI(CPEMI);
- CPE->CPEMI = NULL;
- --NumCPEs;
- return true;
- }
- return false;
-}
-
-/// See if the currently referenced CPE is in range; if not, see if an in-range
-/// clone of the CPE is in range, and if so, change the data structures so the
-/// user references the clone. Returns:
-/// 0 = no existing entry found
-/// 1 = entry found, and there were no code insertions or deletions
-/// 2 = entry found, and there were code insertions or deletions
-int AArch64ConstantIslands::findInRangeCPEntry(CPUser& U, unsigned UserOffset)
-{
- MachineInstr *UserMI = U.MI;
- MachineInstr *CPEMI = U.CPEMI;
-
- // Check to see if the CPE is already in-range.
- if (isCPEntryInRange(UserMI, UserOffset, CPEMI, U.getOffsetBits(), true)) {
- DEBUG(dbgs() << "In range\n");
- return 1;
- }
-
- // No. Look for previously created clones of the CPE that are in range.
- unsigned CPI = CPEMI->getOperand(1).getIndex();
- std::vector<CPEntry> &CPEs = CPEntries[CPI];
- for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
- // We already tried this one
- if (CPEs[i].CPEMI == CPEMI)
- continue;
- // Removing CPEs can leave empty entries, skip
- if (CPEs[i].CPEMI == NULL)
- continue;
- if (isCPEntryInRange(UserMI, UserOffset, CPEs[i].CPEMI,
- U.getOffsetBits())) {
- DEBUG(dbgs() << "Replacing CPE#" << CPI << " with CPE#"
- << CPEs[i].CPI << "\n");
- // Point the CPUser node to the replacement
- U.CPEMI = CPEs[i].CPEMI;
- // Change the CPI in the instruction operand to refer to the clone.
- for (unsigned j = 0, e = UserMI->getNumOperands(); j != e; ++j)
- if (UserMI->getOperand(j).isCPI()) {
- UserMI->getOperand(j).setIndex(CPEs[i].CPI);
- break;
- }
- // Adjust the refcount of the clone...
- CPEs[i].RefCount++;
- // ...and the original. If we didn't remove the old entry, none of the
- // addresses changed, so we don't need another pass.
- return decrementCPEReferenceCount(CPI, CPEMI) ? 2 : 1;
- }
- }
- return 0;
-}
-
-/// Look for an existing entry in the WaterList in which we can place the CPE
-/// referenced from U so it's within range of U's MI. Returns true if found,
-/// false if not. If it returns true, WaterIter is set to the WaterList
-/// entry. To ensure that this pass terminates, the CPE location for a
-/// particular CPUser is only allowed to move to a lower address, so search
-/// backward from the end of the list and prefer the first water that is in
-/// range.
-bool AArch64ConstantIslands::findAvailableWater(CPUser &U, unsigned UserOffset,
- water_iterator &WaterIter) {
- if (WaterList.empty())
- return false;
-
- unsigned BestGrowth = ~0u;
- for (water_iterator IP = prior(WaterList.end()), B = WaterList.begin();;
- --IP) {
- MachineBasicBlock* WaterBB = *IP;
- // Check if water is in range and is either at a lower address than the
- // current "high water mark" or a new water block that was created since
- // the previous iteration by inserting an unconditional branch. In the
- // latter case, we want to allow resetting the high water mark back to
- // this new water since we haven't seen it before. Inserting branches
- // should be relatively uncommon and when it does happen, we want to be
- // sure to take advantage of it for all the CPEs near that block, so that
- // we don't insert more branches than necessary.
- unsigned Growth;
- if (isWaterInRange(UserOffset, WaterBB, U, Growth) &&
- (WaterBB->getNumber() < U.HighWaterMark->getNumber() ||
- NewWaterList.count(WaterBB)) && Growth < BestGrowth) {
- // This is the least amount of required padding seen so far.
- BestGrowth = Growth;
- WaterIter = IP;
- DEBUG(dbgs() << "Found water after BB#" << WaterBB->getNumber()
- << " Growth=" << Growth << '\n');
-
- // Keep looking unless it is perfect.
- if (BestGrowth == 0)
- return true;
- }
- if (IP == B)
- break;
- }
- return BestGrowth != ~0u;
-}
-
-/// No existing WaterList entry will work for CPUsers[CPUserIndex], so create a
-/// place to put the CPE. The end of the block is used if in range, and the
-/// conditional branch munged so control flow is correct. Otherwise the block
-/// is split to create a hole with an unconditional branch around it. In either
-/// case NewMBB is set to a block following which the new island can be inserted
-/// (the WaterList is not adjusted).
-void AArch64ConstantIslands::createNewWater(unsigned CPUserIndex,
- unsigned UserOffset,
- MachineBasicBlock *&NewMBB) {
- CPUser &U = CPUsers[CPUserIndex];
- MachineInstr *UserMI = U.MI;
- MachineInstr *CPEMI = U.CPEMI;
- unsigned CPELogAlign = getCPELogAlign(CPEMI);
- MachineBasicBlock *UserMBB = UserMI->getParent();
- const BasicBlockInfo &UserBBI = BBInfo[UserMBB->getNumber()];
-
- // If the block does not end in an unconditional branch already, and if the
- // end of the block is within range, make new water there.
- if (BBHasFallthrough(UserMBB)) {
- // Size of branch to insert.
- unsigned InstrSize = 4;
- // Compute the offset where the CPE will begin.
- unsigned CPEOffset = UserBBI.postOffset(CPELogAlign) + InstrSize;
-
- if (isOffsetInRange(UserOffset, CPEOffset, U)) {
- DEBUG(dbgs() << "Split at end of BB#" << UserMBB->getNumber()
- << format(", expected CPE offset %#x\n", CPEOffset));
- NewMBB = llvm::next(MachineFunction::iterator(UserMBB));
- // Add an unconditional branch from UserMBB to fallthrough block. Record
- // it for branch lengthening; this new branch will not get out of range,
- // but if the preceding conditional branch is out of range, the targets
- // will be exchanged, and the altered branch may be out of range, so the
- // machinery has to know about it.
- BuildMI(UserMBB, DebugLoc(), TII->get(AArch64::Bimm)).addMBB(NewMBB);
-
- // 26 bits written down, specifying a multiple of 4.
- unsigned OffsetBits = 26 + 2;
- ImmBranches.push_back(ImmBranch(&UserMBB->back(), OffsetBits, false));
- BBInfo[UserMBB->getNumber()].Size += InstrSize;
- adjustBBOffsetsAfter(UserMBB);
- return;
- }
- }
-
- // What a big block. Find a place within the block to split it. We make a
- // first guess, then walk through the instructions between the one currently
- // being looked at and the possible insertion point, and make sure any other
- // instructions that reference CPEs will be able to use the same island area;
- // if not, we back up the insertion point.
-
- // Try to split the block so it's fully aligned. Compute the latest split
- // point where we can add a 4-byte branch instruction, and then align to
- // LogAlign which is the largest possible alignment in the function.
- unsigned LogAlign = MF->getAlignment();
- assert(LogAlign >= CPELogAlign && "Over-aligned constant pool entry");
- unsigned KnownBits = UserBBI.internalKnownBits();
- unsigned UPad = UnknownPadding(LogAlign, KnownBits);
- unsigned BaseInsertOffset = UserOffset + U.getMaxPosDisp() - UPad;
- DEBUG(dbgs() << format("Split in middle of big block before %#x",
- BaseInsertOffset));
-
- // The 4 in the following is for the unconditional branch we'll be inserting
- // Alignment of the island is handled inside isOffsetInRange.
- BaseInsertOffset -= 4;
-
- DEBUG(dbgs() << format(", adjusted to %#x", BaseInsertOffset)
- << " la=" << LogAlign
- << " kb=" << KnownBits
- << " up=" << UPad << '\n');
-
- // This could point off the end of the block if we've already got constant
- // pool entries following this block; only the last one is in the water list.
- // Back past any possible branches (allow for a conditional and a maximally
- // long unconditional).
- if (BaseInsertOffset + 8 >= UserBBI.postOffset()) {
- BaseInsertOffset = UserBBI.postOffset() - UPad - 8;
- DEBUG(dbgs() << format("Move inside block: %#x\n", BaseInsertOffset));
- }
- unsigned EndInsertOffset = BaseInsertOffset + 4 + UPad +
- CPEMI->getOperand(2).getImm();
- MachineBasicBlock::iterator MI = UserMI;
- ++MI;
- unsigned CPUIndex = CPUserIndex+1;
- unsigned NumCPUsers = CPUsers.size();
- for (unsigned Offset = UserOffset+TII->getInstSizeInBytes(*UserMI);
- Offset < BaseInsertOffset;
- Offset += TII->getInstSizeInBytes(*MI),
- MI = llvm::next(MI)) {
- assert(MI != UserMBB->end() && "Fell off end of block");
- if (CPUIndex < NumCPUsers && CPUsers[CPUIndex].MI == MI) {
- CPUser &U = CPUsers[CPUIndex];
- if (!isOffsetInRange(Offset, EndInsertOffset, U)) {
- // Shift intertion point by one unit of alignment so it is within reach.
- BaseInsertOffset -= 1u << LogAlign;
- EndInsertOffset -= 1u << LogAlign;
- }
- // This is overly conservative, as we don't account for CPEMIs being
- // reused within the block, but it doesn't matter much. Also assume CPEs
- // are added in order with alignment padding. We may eventually be able
- // to pack the aligned CPEs better.
- EndInsertOffset += U.CPEMI->getOperand(2).getImm();
- CPUIndex++;
- }
- }
-
- --MI;
- NewMBB = splitBlockBeforeInstr(MI);
-}
-
-/// Analyze the specified user, checking to see if it is out-of-range. If so,
-/// pick up the constant pool value and move it some place in-range. Return
-/// true if we changed any addresses, false otherwise.
-bool AArch64ConstantIslands::handleConstantPoolUser(unsigned CPUserIndex) {
- CPUser &U = CPUsers[CPUserIndex];
- MachineInstr *UserMI = U.MI;
- MachineInstr *CPEMI = U.CPEMI;
- unsigned CPI = CPEMI->getOperand(1).getIndex();
- unsigned Size = CPEMI->getOperand(2).getImm();
- // Compute this only once, it's expensive.
- unsigned UserOffset = getUserOffset(U);
-
- // See if the current entry is within range, or there is a clone of it
- // in range.
- int result = findInRangeCPEntry(U, UserOffset);
- if (result==1) return false;
- else if (result==2) return true;
-
- // No existing clone of this CPE is within range.
- // We will be generating a new clone. Get a UID for it.
- unsigned ID = AFI->createPICLabelUId();
-
- // Look for water where we can place this CPE.
- MachineBasicBlock *NewIsland = MF->CreateMachineBasicBlock();
- MachineBasicBlock *NewMBB;
- water_iterator IP;
- if (findAvailableWater(U, UserOffset, IP)) {
- DEBUG(dbgs() << "Found water in range\n");
- MachineBasicBlock *WaterBB = *IP;
-
- // If the original WaterList entry was "new water" on this iteration,
- // propagate that to the new island. This is just keeping NewWaterList
- // updated to match the WaterList, which will be updated below.
- if (NewWaterList.count(WaterBB)) {
- NewWaterList.erase(WaterBB);
- NewWaterList.insert(NewIsland);
- }
- // The new CPE goes before the following block (NewMBB).
- NewMBB = llvm::next(MachineFunction::iterator(WaterBB));
-
- } else {
- // No water found.
- DEBUG(dbgs() << "No water found\n");
- createNewWater(CPUserIndex, UserOffset, NewMBB);
-
- // splitBlockBeforeInstr adds to WaterList, which is important when it is
- // called while handling branches so that the water will be seen on the
- // next iteration for constant pools, but in this context, we don't want
- // it. Check for this so it will be removed from the WaterList.
- // Also remove any entry from NewWaterList.
- MachineBasicBlock *WaterBB = prior(MachineFunction::iterator(NewMBB));
- IP = std::find(WaterList.begin(), WaterList.end(), WaterBB);
- if (IP != WaterList.end())
- NewWaterList.erase(WaterBB);
-
- // We are adding new water. Update NewWaterList.
- NewWaterList.insert(NewIsland);
- }
-
- // Remove the original WaterList entry; we want subsequent insertions in
- // this vicinity to go after the one we're about to insert. This
- // considerably reduces the number of times we have to move the same CPE
- // more than once and is also important to ensure the algorithm terminates.
- if (IP != WaterList.end())
- WaterList.erase(IP);
-
- // Okay, we know we can put an island before NewMBB now, do it!
- MF->insert(NewMBB, NewIsland);
-
- // Update internal data structures to account for the newly inserted MBB.
- updateForInsertedWaterBlock(NewIsland);
-
- // Decrement the old entry, and remove it if refcount becomes 0.
- decrementCPEReferenceCount(CPI, CPEMI);
-
- // Now that we have an island to add the CPE to, clone the original CPE and
- // add it to the island.
- U.HighWaterMark = NewIsland;
- U.CPEMI = BuildMI(NewIsland, DebugLoc(), TII->get(AArch64::CONSTPOOL_ENTRY))
- .addImm(ID).addConstantPoolIndex(CPI).addImm(Size);
- CPEntries[CPI].push_back(CPEntry(U.CPEMI, ID, 1));
- ++NumCPEs;
-
- // Mark the basic block as aligned as required by the const-pool entry.
- NewIsland->setAlignment(getCPELogAlign(U.CPEMI));
-
- // Increase the size of the island block to account for the new entry.
- BBInfo[NewIsland->getNumber()].Size += Size;
- adjustBBOffsetsAfter(llvm::prior(MachineFunction::iterator(NewIsland)));
-
- // Finally, change the CPI in the instruction operand to be ID.
- for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)
- if (UserMI->getOperand(i).isCPI()) {
- UserMI->getOperand(i).setIndex(ID);
- break;
- }
-
- DEBUG(dbgs() << " Moved CPE to #" << ID << " CPI=" << CPI
- << format(" offset=%#x\n", BBInfo[NewIsland->getNumber()].Offset));
-
- return true;
-}
-
-/// Remove a dead constant pool entry instruction. Update sizes and offsets of
-/// impacted basic blocks.
-void AArch64ConstantIslands::removeDeadCPEMI(MachineInstr *CPEMI) {
- MachineBasicBlock *CPEBB = CPEMI->getParent();
- unsigned Size = CPEMI->getOperand(2).getImm();
- CPEMI->eraseFromParent();
- BBInfo[CPEBB->getNumber()].Size -= Size;
- // All succeeding offsets have the current size value added in, fix this.
- if (CPEBB->empty()) {
- BBInfo[CPEBB->getNumber()].Size = 0;
-
- // This block no longer needs to be aligned. <rdar://problem/10534709>.
- CPEBB->setAlignment(0);
- } else
- // Entries are sorted by descending alignment, so realign from the front.
- CPEBB->setAlignment(getCPELogAlign(CPEBB->begin()));
-
- adjustBBOffsetsAfter(CPEBB);
- // An island has only one predecessor BB and one successor BB. Check if
- // this BB's predecessor jumps directly to this BB's successor. This
- // shouldn't happen currently.
- assert(!BBIsJumpedOver(CPEBB) && "How did this happen?");
- // FIXME: remove the empty blocks after all the work is done?
-}
-
-/// Remove constant pool entries whose refcounts are zero.
-bool AArch64ConstantIslands::removeUnusedCPEntries() {
- unsigned MadeChange = false;
- for (unsigned i = 0, e = CPEntries.size(); i != e; ++i) {
- std::vector<CPEntry> &CPEs = CPEntries[i];
- for (unsigned j = 0, ee = CPEs.size(); j != ee; ++j) {
- if (CPEs[j].RefCount == 0 && CPEs[j].CPEMI) {
- removeDeadCPEMI(CPEs[j].CPEMI);
- CPEs[j].CPEMI = NULL;
- MadeChange = true;
- }
- }
- }
- return MadeChange;
-}
-
-/// Returns true if the distance between specific MI and specific BB can fit in
-/// MI's displacement field.
-bool AArch64ConstantIslands::isBBInRange(MachineInstr *MI,
- MachineBasicBlock *DestBB,
- unsigned OffsetBits) {
- int64_t BrOffset = getOffsetOf(MI);
- int64_t DestOffset = BBInfo[DestBB->getNumber()].Offset;
-
- DEBUG(dbgs() << "Branch of destination BB#" << DestBB->getNumber()
- << " from BB#" << MI->getParent()->getNumber()
- << " bits available=" << OffsetBits
- << " from " << getOffsetOf(MI) << " to " << DestOffset
- << " offset " << int(DestOffset-BrOffset) << "\t" << *MI);
-
- return isIntN(OffsetBits, DestOffset - BrOffset);
-}
-
-/// Fix up an immediate branch whose destination is too far away to fit in its
-/// displacement field.
-bool AArch64ConstantIslands::fixupImmediateBr(ImmBranch &Br) {
- MachineInstr *MI = Br.MI;
- MachineBasicBlock *DestBB = 0;
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- if (MI->getOperand(i).isMBB()) {
- DestBB = MI->getOperand(i).getMBB();
- break;
- }
- }
- assert(DestBB && "Branch with no destination BB?");
-
- // Check to see if the DestBB is already in-range.
- if (isBBInRange(MI, DestBB, Br.OffsetBits))
- return false;
-
- assert(Br.IsCond && "Only conditional branches should need fixup");
- return fixupConditionalBr(Br);
-}
-
-/// Fix up a conditional branch whose destination is too far away to fit in its
-/// displacement field. It is converted to an inverse conditional branch + an
-/// unconditional branch to the destination.
-bool
-AArch64ConstantIslands::fixupConditionalBr(ImmBranch &Br) {
- MachineInstr *MI = Br.MI;
- MachineBasicBlock *MBB = MI->getParent();
- unsigned CondBrMBBOperand = 0;
-
- // The general idea is to add an unconditional branch to the destination and
- // invert the conditional branch to jump over it. Complications occur around
- // fallthrough and unreachable ends to the block.
- // b.lt L1
- // =>
- // b.ge L2
- // b L1
- // L2:
-
- // First we invert the conditional branch, by creating a replacement if
- // necessary. This if statement contains all the special handling of different
- // branch types.
- if (MI->getOpcode() == AArch64::Bcc) {
- // The basic block is operand number 1 for Bcc
- CondBrMBBOperand = 1;
-
- A64CC::CondCodes CC = (A64CC::CondCodes)MI->getOperand(0).getImm();
- CC = A64InvertCondCode(CC);
- MI->getOperand(0).setImm(CC);
- } else {
- MachineInstrBuilder InvertedMI;
- int InvertedOpcode;
- switch (MI->getOpcode()) {
- default: llvm_unreachable("Unknown branch type");
- case AArch64::TBZxii: InvertedOpcode = AArch64::TBNZxii; break;
- case AArch64::TBZwii: InvertedOpcode = AArch64::TBNZwii; break;
- case AArch64::TBNZxii: InvertedOpcode = AArch64::TBZxii; break;
- case AArch64::TBNZwii: InvertedOpcode = AArch64::TBZwii; break;
- case AArch64::CBZx: InvertedOpcode = AArch64::CBNZx; break;
- case AArch64::CBZw: InvertedOpcode = AArch64::CBNZw; break;
- case AArch64::CBNZx: InvertedOpcode = AArch64::CBZx; break;
- case AArch64::CBNZw: InvertedOpcode = AArch64::CBZw; break;
- }
-
- InvertedMI = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(InvertedOpcode));
- for (unsigned i = 0, e= MI->getNumOperands(); i != e; ++i) {
- InvertedMI.addOperand(MI->getOperand(i));
- if (MI->getOperand(i).isMBB())
- CondBrMBBOperand = i;
- }
-
- MI->eraseFromParent();
- MI = Br.MI = InvertedMI;
- }
-
- // If the branch is at the end of its MBB and that has a fall-through block,
- // direct the updated conditional branch to the fall-through
- // block. Otherwise, split the MBB before the next instruction.
- MachineInstr *BMI = &MBB->back();
- bool NeedSplit = (BMI != MI) || !BBHasFallthrough(MBB);
-
- ++NumCBrFixed;
- if (BMI != MI) {
- if (llvm::next(MachineBasicBlock::iterator(MI)) == prior(MBB->end()) &&
- BMI->getOpcode() == AArch64::Bimm) {
- // Last MI in the BB is an unconditional branch. We can swap destinations:
- // b.eq L1 (temporarily b.ne L1 after first change)
- // b L2
- // =>
- // b.ne L2
- // b L1
- MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB();
- if (isBBInRange(MI, NewDest, Br.OffsetBits)) {
- DEBUG(dbgs() << " Invert Bcc condition and swap its destination with "
- << *BMI);
- MachineBasicBlock *DestBB = MI->getOperand(CondBrMBBOperand).getMBB();
- BMI->getOperand(0).setMBB(DestBB);
- MI->getOperand(CondBrMBBOperand).setMBB(NewDest);
- return true;
- }
- }
- }
-
- if (NeedSplit) {
- MachineBasicBlock::iterator MBBI = MI; ++MBBI;
- splitBlockBeforeInstr(MBBI);
- // No need for the branch to the next block. We're adding an unconditional
- // branch to the destination.
- int delta = TII->getInstSizeInBytes(MBB->back());
- BBInfo[MBB->getNumber()].Size -= delta;
- MBB->back().eraseFromParent();
- // BBInfo[SplitBB].Offset is wrong temporarily, fixed below
- }
-
- // After splitting and removing the unconditional branch from the original BB,
- // the structure is now:
- // oldbb:
- // [things]
- // b.invertedCC L1
- // splitbb/fallthroughbb:
- // [old b L2/real continuation]
- //
- // We now have to change the conditional branch to point to splitbb and add an
- // unconditional branch after it to L1, giving the final structure:
- // oldbb:
- // [things]
- // b.invertedCC splitbb
- // b L1
- // splitbb/fallthroughbb:
- // [old b L2/real continuation]
- MachineBasicBlock *NextBB = llvm::next(MachineFunction::iterator(MBB));
-
- DEBUG(dbgs() << " Insert B to BB#"
- << MI->getOperand(CondBrMBBOperand).getMBB()->getNumber()
- << " also invert condition and change dest. to BB#"
- << NextBB->getNumber() << "\n");
-
- // Insert a new unconditional branch and fixup the destination of the
- // conditional one. Also update the ImmBranch as well as adding a new entry
- // for the new branch.
- BuildMI(MBB, DebugLoc(), TII->get(AArch64::Bimm))
- .addMBB(MI->getOperand(CondBrMBBOperand).getMBB());
- MI->getOperand(CondBrMBBOperand).setMBB(NextBB);
-
- BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
-
- // 26 bits written down in Bimm, specifying a multiple of 4.
- unsigned OffsetBits = 26 + 2;
- ImmBranches.push_back(ImmBranch(&MBB->back(), OffsetBits, false));
-
- adjustBBOffsetsAfter(MBB);
- return true;
-}
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp?rev=175258&r1=175257&r2=175258&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp Fri Feb 15 03:33:43 2013
@@ -89,8 +89,8 @@ public:
bool SelectTSTBOperand(SDValue N, SDValue &FixedPos, unsigned RegWidth);
SDNode *TrySelectToMoveImm(SDNode *N);
+ SDNode *LowerToFPLitPool(SDNode *Node);
SDNode *SelectToLitPool(SDNode *N);
- SDNode *SelectToFPLitPool(SDNode *N);
SDNode* Select(SDNode*);
private:
@@ -225,92 +225,78 @@ SDNode *AArch64DAGToDAGISel::TrySelectTo
}
SDNode *AArch64DAGToDAGISel::SelectToLitPool(SDNode *Node) {
- DebugLoc dl = Node->getDebugLoc();
+ DebugLoc DL = Node->getDebugLoc();
uint64_t UnsignedVal = cast<ConstantSDNode>(Node)->getZExtValue();
int64_t SignedVal = cast<ConstantSDNode>(Node)->getSExtValue();
EVT DestType = Node->getValueType(0);
+ EVT PtrVT = TLI.getPointerTy();
// Since we may end up loading a 64-bit constant from a 32-bit entry the
// constant in the pool may have a different type to the eventual node.
- SDValue PoolEntry;
- EVT LoadType;
- unsigned LoadInst;
+ ISD::LoadExtType Extension;
+ EVT MemType;
assert((DestType == MVT::i64 || DestType == MVT::i32)
&& "Only expect integer constants at the moment");
- if (DestType == MVT::i32 || UnsignedVal <= UINT32_MAX) {
- // LDR w3, lbl
- LoadInst = AArch64::LDRw_lit;
- LoadType = MVT::i32;
-
- PoolEntry = CurDAG->getTargetConstantPool(
- ConstantInt::get(Type::getInt32Ty(*CurDAG->getContext()), UnsignedVal),
- MVT::i32);
+ if (DestType == MVT::i32) {
+ Extension = ISD::NON_EXTLOAD;
+ MemType = MVT::i32;
+ } else if (UnsignedVal <= UINT32_MAX) {
+ Extension = ISD::ZEXTLOAD;
+ MemType = MVT::i32;
} else if (SignedVal >= INT32_MIN && SignedVal <= INT32_MAX) {
- // We can use a sign-extending 32-bit load: LDRSW x3, lbl
- LoadInst = AArch64::LDRSWx_lit;
- LoadType = MVT::i64;
-
- PoolEntry = CurDAG->getTargetConstantPool(
- ConstantInt::getSigned(Type::getInt32Ty(*CurDAG->getContext()),
- SignedVal),
- MVT::i32);
+ Extension = ISD::SEXTLOAD;
+ MemType = MVT::i32;
} else {
- // Full 64-bit load needed: LDR x3, lbl
- LoadInst = AArch64::LDRx_lit;
- LoadType = MVT::i64;
-
- PoolEntry = CurDAG->getTargetConstantPool(
- ConstantInt::get(Type::getInt64Ty(*CurDAG->getContext()), UnsignedVal),
- MVT::i64);
- }
-
- SDNode *ResNode = CurDAG->getMachineNode(LoadInst, dl,
- LoadType, MVT::Other,
- PoolEntry, CurDAG->getEntryNode());
-
- if (DestType != LoadType) {
- // We used the implicit zero-extension of "LDR w3, lbl", tell LLVM this
- // fact.
- assert(DestType == MVT::i64 && LoadType == MVT::i32
- && "Unexpected load combination");
-
- ResNode = CurDAG->getMachineNode(TargetOpcode::SUBREG_TO_REG, dl,
- MVT::i64, MVT::i32, MVT::Other,
- CurDAG->getTargetConstant(0, MVT::i64),
- SDValue(ResNode, 0),
- CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32));
+ Extension = ISD::NON_EXTLOAD;
+ MemType = MVT::i64;
}
- return ResNode;
+ Constant *CV = ConstantInt::get(Type::getIntNTy(*CurDAG->getContext(),
+ MemType.getSizeInBits()),
+ UnsignedVal);
+ SDValue PoolAddr;
+ unsigned Alignment = TLI.getDataLayout()->getABITypeAlignment(CV->getType());
+ PoolAddr = CurDAG->getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
+ CurDAG->getTargetConstantPool(CV, PtrVT, 0, 0,
+ AArch64II::MO_NO_FLAG),
+ CurDAG->getTargetConstantPool(CV, PtrVT, 0, 0,
+ AArch64II::MO_LO12),
+ CurDAG->getConstant(Alignment, MVT::i32));
+
+ return CurDAG->getExtLoad(Extension, DL, DestType, CurDAG->getEntryNode(),
+ PoolAddr,
+ MachinePointerInfo::getConstantPool(), MemType,
+ /* isVolatile = */ false,
+ /* isNonTemporal = */ false,
+ Alignment).getNode();
}
-SDNode *AArch64DAGToDAGISel::SelectToFPLitPool(SDNode *Node) {
- DebugLoc dl = Node->getDebugLoc();
+SDNode *AArch64DAGToDAGISel::LowerToFPLitPool(SDNode *Node) {
+ DebugLoc DL = Node->getDebugLoc();
const ConstantFP *FV = cast<ConstantFPSDNode>(Node)->getConstantFPValue();
+ EVT PtrVT = TLI.getPointerTy();
EVT DestType = Node->getValueType(0);
- unsigned LoadInst;
- switch (DestType.getSizeInBits()) {
- case 32:
- LoadInst = AArch64::LDRs_lit;
- break;
- case 64:
- LoadInst = AArch64::LDRd_lit;
- break;
- case 128:
- LoadInst = AArch64::LDRq_lit;
- break;
- default: llvm_unreachable("cannot select floating-point litpool");
- }
-
- SDValue PoolEntry = CurDAG->getTargetConstantPool(FV, DestType);
- SDNode *ResNode = CurDAG->getMachineNode(LoadInst, dl,
- DestType, MVT::Other,
- PoolEntry, CurDAG->getEntryNode());
+ unsigned Alignment = TLI.getDataLayout()->getABITypeAlignment(FV->getType());
+ SDValue PoolAddr;
- return ResNode;
+ assert(TM.getCodeModel() == CodeModel::Small &&
+ "Only small code model supported");
+ PoolAddr = CurDAG->getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
+ CurDAG->getTargetConstantPool(FV, PtrVT, 0, 0,
+ AArch64II::MO_NO_FLAG),
+ CurDAG->getTargetConstantPool(FV, PtrVT, 0, 0,
+ AArch64II::MO_LO12),
+ CurDAG->getConstant(Alignment, MVT::i32));
+
+ return CurDAG->getLoad(DestType, DL, CurDAG->getEntryNode(), PoolAddr,
+ MachinePointerInfo::getConstantPool(),
+ /* isVolatile = */ false,
+ /* isNonTemporal = */ false,
+ /* isInvariant = */ true,
+ Alignment).getNode();
}
bool
@@ -377,17 +363,19 @@ SDNode *AArch64DAGToDAGISel::Select(SDNo
ResNode = TrySelectToMoveImm(Node);
}
- // If even that fails we fall back to a lit-pool entry at the moment. Future
- // tuning or restrictions like non-readable code-sections may mandate a
- // sequence of MOVZ/MOVN/MOVK instructions.
- if (!ResNode) {
- ResNode = SelectToLitPool(Node);
- }
+ if (ResNode)
+ return ResNode;
+ // If even that fails we fall back to a lit-pool entry at the moment. Future
+ // tuning may change this to a sequence of MOVZ/MOVN/MOVK instructions.
+ ResNode = SelectToLitPool(Node);
assert(ResNode && "We need *some* way to materialise a constant");
+ // We want to continue selection at this point since the litpool access
+ // generated used generic nodes for simplicity.
ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
- return NULL;
+ Node = ResNode;
+ break;
}
case ISD::ConstantFP: {
if (A64Imms::isFPImm(cast<ConstantFPSDNode>(Node)->getValueAPF())) {
@@ -395,9 +383,13 @@ SDNode *AArch64DAGToDAGISel::Select(SDNo
break;
}
- SDNode *ResNode = SelectToFPLitPool(Node);
+ SDNode *ResNode = LowerToFPLitPool(Node);
ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
- return NULL;
+
+ // We want to continue selection at this point since the litpool access
+ // generated used generic nodes for simplicity.
+ Node = ResNode;
+ break;
}
default:
break; // Let generic code handle it
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=175258&r1=175257&r2=175258&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Fri Feb 15 03:33:43 2013
@@ -1866,8 +1866,14 @@ AArch64TargetLowering::LowerGlobalAddres
// Weak symbols can't use ADRP/ADD pair since they should evaluate to
// zero when undefined. In PIC mode the GOT can take care of this, but in
// absolute mode we use a constant pool load.
- return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
- DAG.getConstantPool(GV, GN->getValueType(0)),
+ SDValue PoolAddr;
+ PoolAddr = DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT,
+ DAG.getTargetConstantPool(GV, PtrVT, 0, 0,
+ AArch64II::MO_NO_FLAG),
+ DAG.getTargetConstantPool(GV, PtrVT, 0, 0,
+ AArch64II::MO_LO12),
+ DAG.getConstant(8, MVT::i32));
+ return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), PoolAddr,
MachinePointerInfo::getConstantPool(),
/*isVolatile=*/ false, /*isNonTemporal=*/ true,
/*isInvariant=*/ true, 8);
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=175258&r1=175257&r2=175258&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Fri Feb 15 03:33:43 2013
@@ -558,50 +558,6 @@ void AArch64InstrInfo::getAddressConstra
}
}
-unsigned AArch64InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
- const MCInstrDesc &MCID = MI.getDesc();
- const MachineBasicBlock &MBB = *MI.getParent();
- const MachineFunction &MF = *MBB.getParent();
- const MCAsmInfo &MAI = *MF.getTarget().getMCAsmInfo();
-
- if (MCID.getSize())
- return MCID.getSize();
-
- if (MI.getOpcode() == AArch64::INLINEASM)
- return getInlineAsmLength(MI.getOperand(0).getSymbolName(), MAI);
-
- if (MI.isLabel())
- return 0;
-
- switch (MI.getOpcode()) {
- case TargetOpcode::BUNDLE:
- return getInstBundleLength(MI);
- case TargetOpcode::IMPLICIT_DEF:
- case TargetOpcode::KILL:
- case TargetOpcode::PROLOG_LABEL:
- case TargetOpcode::EH_LABEL:
- case TargetOpcode::DBG_VALUE:
- return 0;
- case AArch64::CONSTPOOL_ENTRY:
- return MI.getOperand(2).getImm();
- case AArch64::TLSDESCCALL:
- return 0;
- default:
- llvm_unreachable("Unknown instruction class");
- }
-}
-
-unsigned AArch64InstrInfo::getInstBundleLength(const MachineInstr &MI) const {
- unsigned Size = 0;
- MachineBasicBlock::const_instr_iterator I = MI;
- MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
- while (++I != E && I->isInsideBundle()) {
- assert(!I->isBundle() && "No nested bundle!");
- Size += getInstSizeInBytes(*I);
- }
- return Size;
-}
-
bool llvm::rewriteA64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
unsigned FrameReg, int &Offset,
const AArch64InstrInfo &TII) {
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h?rev=175258&r1=175257&r2=175258&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h Fri Feb 15 03:33:43 2013
@@ -83,10 +83,6 @@ public:
/// + imm % OffsetScale == 0
void getAddressConstraints(const MachineInstr &MI, int &AccessScale,
int &MinOffset, int &MaxOffset) const;
-
- unsigned getInstSizeInBytes(const MachineInstr &MI) const;
-
- unsigned getInstBundleLength(const MachineInstr &MI) const;
};
bool rewriteA64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=175258&r1=175257&r2=175258&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Fri Feb 15 03:33:43 2013
@@ -2449,16 +2449,12 @@ class A64I_LDRlitSimple<bits<2> opc, bit
"ldr\t$Rt, $Imm19", patterns, NoItinerary>;
let mayLoad = 1 in {
- def LDRw_lit : A64I_LDRlitSimple<0b00, 0b0, GPR32,
- [(set (i32 GPR32:$Rt), (load constpool:$Imm19))]>;
- def LDRx_lit : A64I_LDRlitSimple<0b01, 0b0, GPR64,
- [(set (i64 GPR64:$Rt), (load constpool:$Imm19))]>;
+ def LDRw_lit : A64I_LDRlitSimple<0b00, 0b0, GPR32>;
+ def LDRx_lit : A64I_LDRlitSimple<0b01, 0b0, GPR64>;
}
-def LDRs_lit : A64I_LDRlitSimple<0b00, 0b1, FPR32,
- [(set (f32 FPR32:$Rt), (load constpool:$Imm19))]>;
-def LDRd_lit : A64I_LDRlitSimple<0b01, 0b1, FPR64,
- [(set (f64 FPR64:$Rt), (load constpool:$Imm19))]>;
+def LDRs_lit : A64I_LDRlitSimple<0b00, 0b1, FPR32>;
+def LDRd_lit : A64I_LDRlitSimple<0b01, 0b1, FPR64>;
let mayLoad = 1 in {
def LDRq_lit : A64I_LDRlitSimple<0b10, 0b1, FPR128>;
@@ -4565,22 +4561,6 @@ def : Pat<(and (A64Bfi GPR64:$src, GPR64
}
//===----------------------------------------------------------------------===//
-// Constant island entries
-//===----------------------------------------------------------------------===//
-
-// The constant island pass needs to create "instructions" in the middle of the
-// instruction stream to reresent its constants.
-
-def cpinst_operand : Operand<i32>;
-
-def CONSTPOOL_ENTRY : PseudoInst<(outs), (ins cpinst_operand:$instid,
- cpinst_operand:$cpidx,
- i32imm:$size), []> {
- let hasSideEffects = 0;
- let isNotDuplicable = 1;
-}
-
-//===----------------------------------------------------------------------===//
// Miscellaneous patterns
//===----------------------------------------------------------------------===//
@@ -4898,6 +4878,8 @@ defm : uimm12_pats<(A64WrapperSmall text
ALIGN),
(ADRPxi texternalsym:$Hi), (i64 texternalsym:$Lo12)>;
+defm : uimm12_pats<(A64WrapperSmall tconstpool:$Hi, tconstpool:$Lo12, ALIGN),
+ (ADRPxi tconstpool:$Hi), (i64 tconstpool:$Lo12)>;
// We also want to use uimm12 instructions for local variables at the moment.
def tframeindex_XFORM : SDNodeXForm<frameindex, [{
Modified: llvm/trunk/lib/Target/AArch64/AArch64MachineFunctionInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64MachineFunctionInfo.h?rev=175258&r1=175257&r2=175258&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64MachineFunctionInfo.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64MachineFunctionInfo.h Fri Feb 15 03:33:43 2013
@@ -14,7 +14,6 @@
#ifndef AARCH64MACHINEFUNCTIONINFO_H
#define AARCH64MACHINEFUNCTIONINFO_H
-#include "llvm/ADT/DenseMap.h"
#include "llvm/CodeGen/MachineFunction.h"
namespace llvm {
@@ -49,10 +48,6 @@ class AArch64MachineFunctionInfo : publi
/// Number of local-dynamic TLS accesses.
unsigned NumLocalDynamics;
- /// Keep track of the next label to be created within this function to
- /// represent a cloned constant pool entry. Used by constant islands pass.
- unsigned PICLabelUId;
-
/// @see AArch64 Procedure Call Standard, B.3
///
/// The Frame index of the area where LowerFormalArguments puts the
@@ -96,7 +91,6 @@ public:
ArgumentStackToRestore(0),
InitialStackAdjust(0),
NumLocalDynamics(0),
- PICLabelUId(0),
VariadicGPRIdx(0),
VariadicGPRSize(0),
VariadicFPRIdx(0),
@@ -109,7 +103,6 @@ public:
ArgumentStackToRestore(0),
InitialStackAdjust(0),
NumLocalDynamics(0),
- PICLabelUId(0),
VariadicGPRIdx(0),
VariadicGPRSize(0),
VariadicFPRIdx(0),
@@ -131,10 +124,6 @@ public:
unsigned getNumLocalDynamicTLSAccesses() const { return NumLocalDynamics; }
void incNumLocalDynamicTLSAccesses() { ++NumLocalDynamics; }
- void initPICLabelUId(unsigned UId) { PICLabelUId = UId; }
- unsigned getNumPICLabels() const { return PICLabelUId; }
- unsigned createPICLabelUId() { return PICLabelUId++; }
-
int getVariadicGPRIdx() const { return VariadicGPRIdx; }
void setVariadicGPRIdx(int Idx) { VariadicGPRIdx = Idx; }
Modified: llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp?rev=175258&r1=175257&r2=175258&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp Fri Feb 15 03:33:43 2013
@@ -66,7 +66,6 @@ TargetPassConfig *AArch64TargetMachine::
bool AArch64PassConfig::addPreEmitPass() {
addPass(&UnpackMachineBundlesID);
- addPass(createAArch64ConstantIslandPass());
return true;
}
Modified: llvm/trunk/lib/Target/AArch64/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/CMakeLists.txt?rev=175258&r1=175257&r2=175258&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/AArch64/CMakeLists.txt Fri Feb 15 03:33:43 2013
@@ -14,7 +14,6 @@ add_public_tablegen_target(AArch64Common
add_llvm_target(AArch64CodeGen
AArch64AsmPrinter.cpp
- AArch64ConstantIslandPass.cpp
AArch64FrameLowering.cpp
AArch64ISelDAGToDAG.cpp
AArch64ISelLowering.cpp
Modified: llvm/trunk/test/CodeGen/AArch64/adrp-relocation.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/adrp-relocation.ll?rev=175258&r1=175257&r2=175258&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/adrp-relocation.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/adrp-relocation.ll Fri Feb 15 03:33:43 2013
@@ -1,16 +1,16 @@
; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -filetype=obj < %s | elf-dump | FileCheck %s
-define fp128 @testfn() nounwind {
+define i64 @testfn() nounwind {
entry:
- ret fp128 0xL00000000000000004004500000000000
+ ret i64 0
}
-define fp128 @foo() nounwind {
+define i64 @foo() nounwind {
entry:
- %bar = alloca fp128 ()*, align 8
- store fp128 ()* @testfn, fp128 ()** %bar, align 8
- %call = call fp128 @testfn()
- ret fp128 %call
+ %bar = alloca i64 ()*, align 8
+ store i64 ()* @testfn, i64 ()** %bar, align 8
+ %call = call i64 @testfn()
+ ret i64 %call
}
; The above should produce an ADRP/ADD pair to calculate the address of
@@ -22,14 +22,14 @@ entry:
; CHECK: .rela.text
; CHECK: # Relocation 0
-; CHECK-NEXT: (('r_offset', 0x0000000000000028)
-; CHECK-NEXT: ('r_sym', 0x00000009)
+; CHECK-NEXT: (('r_offset', 0x0000000000000010)
+; CHECK-NEXT: ('r_sym', 0x00000007)
; CHECK-NEXT: ('r_type', 0x00000113)
; CHECK-NEXT: ('r_addend', 0x0000000000000000)
; CHECK-NEXT: ),
; CHECK-NEXT: Relocation 1
-; CHECK-NEXT: (('r_offset', 0x000000000000002c)
-; CHECK-NEXT: ('r_sym', 0x00000009)
+; CHECK-NEXT: (('r_offset', 0x0000000000000014)
+; CHECK-NEXT: ('r_sym', 0x00000007)
; CHECK-NEXT: ('r_type', 0x00000115)
; CHECK-NEXT: ('r_addend', 0x0000000000000000)
; CHECK-NEXT: ),
Modified: llvm/trunk/test/CodeGen/AArch64/extern-weak.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/extern-weak.ll?rev=175258&r1=175257&r2=175258&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/extern-weak.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/extern-weak.ll Fri Feb 15 03:33:43 2013
@@ -6,8 +6,9 @@ define i32()* @foo() {
; The usual ADRP/ADD pair can't be used for a weak reference because it must
; evaluate to 0 if the symbol is undefined. We use a litpool entry.
ret i32()* @var
-; CHECK: ldr x0, .LCPI0_0
-
; CHECK: .LCPI0_0:
; CHECK-NEXT: .xword var
+
+; CHECK: ldr x0, [{{x[0-9]+}}, #:lo12:.LCPI0_0]
+
}
Modified: llvm/trunk/test/CodeGen/AArch64/fp-cond-sel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fp-cond-sel.ll?rev=175258&r1=175257&r2=175258&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/fp-cond-sel.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/fp-cond-sel.ll Fri Feb 15 03:33:43 2013
@@ -9,15 +9,15 @@ define void @test_csel(i32 %lhs32, i32 %
%tst1 = icmp ugt i32 %lhs32, %rhs32
%val1 = select i1 %tst1, float 0.0, float 1.0
store float %val1, float* @varfloat
+; CHECK: ldr [[FLT0:s[0-9]+]], [{{x[0-9]+}}, #:lo12:.LCPI
; CHECK: fmov [[FLT1:s[0-9]+]], #1.0
-; CHECK: ldr [[FLT0:s[0-9]+]], .LCPI
; CHECK: fcsel {{s[0-9]+}}, [[FLT0]], [[FLT1]], hi
%rhs64 = sext i32 %rhs32 to i64
%tst2 = icmp sle i64 %lhs64, %rhs64
%val2 = select i1 %tst2, double 1.0, double 0.0
store double %val2, double* @vardouble
-; CHECK: ldr [[FLT0:d[0-9]+]], .LCPI
+; CHECK: ldr [[FLT0:d[0-9]+]], [{{x[0-9]+}}, #:lo12:.LCPI
; CHECK: fmov [[FLT1:d[0-9]+]], #1.0
; CHECK: fcsel {{d[0-9]+}}, [[FLT1]], [[FLT0]], le
Modified: llvm/trunk/test/CodeGen/AArch64/fp128-folding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fp128-folding.ll?rev=175258&r1=175257&r2=175258&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/fp128-folding.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/fp128-folding.ll Fri Feb 15 03:33:43 2013
@@ -12,6 +12,6 @@ define fp128 @test_folding() {
%fpval = sitofp i32 %val to fp128
; If the value is loaded from a constant pool into an fp128, it's been folded
; successfully.
-; CHECK: ldr {{q[0-9]+}}, .LCPI
+; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, #:lo12:.LCPI
ret fp128 %fpval
}
\ No newline at end of file
Modified: llvm/trunk/test/CodeGen/AArch64/fp128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fp128.ll?rev=175258&r1=175257&r2=175258&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/fp128.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/fp128.ll Fri Feb 15 03:33:43 2013
@@ -261,6 +261,10 @@ define void @test_extend() {
}
define fp128 @test_neg(fp128 %in) {
+; CHECK: [[MINUS0:.LCPI[0-9]+_0]]:
+; Make sure the weird hex constant below *is* -0.0
+; CHECK-NEXT: fp128 -0
+
; CHECK: test_neg:
; Could in principle be optimized to fneg which we can't select, this makes
@@ -268,13 +272,9 @@ define fp128 @test_neg(fp128 %in) {
%ret = fsub fp128 0xL00000000000000008000000000000000, %in
; CHECK: str q0, [sp, #-16]
; CHECK-NEXT: ldr q1, [sp], #16
-; CHECK: ldr q0, [[MINUS0:.LCPI[0-9]+_0]]
+; CHECK: ldr q0, [{{x[0-9]+}}, #:lo12:[[MINUS0]]]
; CHECK: bl __subtf3
ret fp128 %ret
; CHECK: ret
-
-; CHECK: [[MINUS0]]:
-; Make sure the weird hex constant below *is* -0.0
-; CHECK-NEXT: fp128 -0
}
Modified: llvm/trunk/test/CodeGen/AArch64/fpimm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fpimm.ll?rev=175258&r1=175257&r2=175258&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/fpimm.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/fpimm.ll Fri Feb 15 03:33:43 2013
@@ -13,7 +13,7 @@ define void @check_float() {
%newval2 = fadd float %val, 128.0
store volatile float %newval2, float* @varf32
-; CHECK: ldr {{s[0-9]+}}, .LCPI0_0
+; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, #:lo12:.LCPI0_0
ret void
}
@@ -28,7 +28,7 @@ define void @check_double() {
%newval2 = fadd double %val, 128.0
store volatile double %newval2, double* @varf64
-; CHECK: ldr {{d[0-9]+}}, .LCPI1_0
+; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, #:lo12:.LCPI1_0
ret void
}
Modified: llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll?rev=175258&r1=175257&r2=175258&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll Fri Feb 15 03:33:43 2013
@@ -83,7 +83,7 @@ define i32 @return_int() {
define double @return_double() {
; CHECK: return_double:
ret double 3.14
-; CHECK: ldr d0, .LCPI
+; CHECK: ldr d0, [{{x[0-9]+}}, #:lo12:.LCPI
}
; This is the kind of IR clang will produce for returning a struct
Modified: llvm/trunk/test/CodeGen/AArch64/func-calls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/func-calls.ll?rev=175258&r1=175257&r2=175258&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/func-calls.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/func-calls.ll Fri Feb 15 03:33:43 2013
@@ -90,7 +90,7 @@ define void @check_stack_args() {
call void @stacked_fpu(float -1.0, double 1.0, float 4.0, float 2.0,
float -2.0, float -8.0, float 16.0, float 1.0,
float 64.0)
-; CHECK: ldr s[[STACKEDREG:[0-9]+]], .LCPI
+; CHECK: ldr s[[STACKEDREG:[0-9]+]], [{{x[0-9]+}}, #:lo12:.LCPI
; CHECK: mov x0, sp
; CHECK: str d[[STACKEDREG]], [x0]
; CHECK bl stacked_fpu
Modified: llvm/trunk/test/CodeGen/AArch64/literal_pools.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/literal_pools.ll?rev=175258&r1=175257&r2=175258&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/literal_pools.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/literal_pools.ll Fri Feb 15 03:33:43 2013
@@ -10,19 +10,23 @@ define void @foo() {
%val32_lit32 = and i32 %val32, 123456785
store volatile i32 %val32_lit32, i32* @var32
-; CHECK: ldr {{w[0-9]+}}, .LCPI0
+; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI0_[0-9]+]]
+; CHECK: ldr {{w[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]]
%val64_lit32 = and i64 %val64, 305402420
store volatile i64 %val64_lit32, i64* @var64
-; CHECK: ldr {{w[0-9]+}}, .LCPI0
+; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI0_[0-9]+]]
+; CHECK: ldr {{w[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]]
%val64_lit32signed = and i64 %val64, -12345678
store volatile i64 %val64_lit32signed, i64* @var64
-; CHECK: ldrsw {{x[0-9]+}}, .LCPI0
+; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI0_[0-9]+]]
+; CHECK: ldrsw {{x[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]]
%val64_lit64 = and i64 %val64, 1234567898765432
store volatile i64 %val64_lit64, i64* @var64
-; CHECK: ldr {{x[0-9]+}}, .LCPI0
+; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI0_[0-9]+]]
+; CHECK: ldr {{x[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]]
ret void
}
@@ -35,13 +39,15 @@ define void @floating_lits() {
%floatval = load float* @varfloat
%newfloat = fadd float %floatval, 128.0
-; CHECK: ldr {{s[0-9]+}}, .LCPI1
+; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI1_[0-9]+]]
+; CHECK: ldr {{s[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]]
; CHECK: fadd
store float %newfloat, float* @varfloat
%doubleval = load double* @vardouble
%newdouble = fadd double %doubleval, 129.0
-; CHECK: ldr {{d[0-9]+}}, .LCPI1
+; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI1_[0-9]+]]
+; CHECK: ldr {{d[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]]
; CHECK: fadd
store double %newdouble, double* @vardouble
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